14f14f9a62
The nullStaticInstPtr was low overhead, but the nopStaticInstPtr needed an actual StaticInst implementation it could point to, and that brought with it some (minor) additional dependencies. Specifically, the implementation of advancePC needs the definition of TheISA::PCState, while all other signatures/impementations in StaticInst are already passing around that type by reference or could be made to, reducing dependencies further. Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42968 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
732 lines
26 KiB
C++
732 lines
26 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013, 2016-2019 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARM_FAULTS_HH__
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#define __ARM_FAULTS_HH__
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#include "arch/arm/pagetable.hh"
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#include "arch/arm/regs/misc.hh"
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#include "arch/arm/types.hh"
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#include "base/logging.hh"
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#include "cpu/null_static_inst.hh"
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#include "sim/faults.hh"
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#include "sim/full_system.hh"
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// The design of the "name" and "vect" functions is in sim/faults.hh
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namespace ArmISA
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{
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typedef Addr FaultOffset;
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class ArmStaticInst;
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class ArmFault : public FaultBase
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{
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protected:
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ExtMachInst machInst;
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uint32_t issRaw;
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// Helper variables for ARMv8 exception handling
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bool bStep; // True if the Arm Faul exception is a software Step exception
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bool from64; // True if the exception is generated from the AArch64 state
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bool to64; // True if the exception is taken in AArch64 state
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ExceptionLevel fromEL; // Source exception level
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ExceptionLevel toEL; // Target exception level
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OperatingMode fromMode; // Source operating mode (aarch32)
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OperatingMode toMode; // Next operating mode (aarch32)
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// This variable is true if the above fault specific informations
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// have been updated. This is to prevent that a client is using their
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// un-updated default constructed value.
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bool faultUpdated;
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bool hypRouted; // True if the fault has been routed to Hypervisor
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bool span; // True if the fault is setting the PSTATE.PAN bit
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virtual Addr getVector(ThreadContext *tc);
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Addr getVector64(ThreadContext *tc);
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public:
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/// Generic fault source enums used to index into
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/// {short/long/aarch64}DescFaultSources[] to get the actual encodings based
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/// on the current register width state and the translation table format in
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/// use
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enum FaultSource
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{
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AlignmentFault = 0,
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InstructionCacheMaintenance, // Short-desc. format only
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SynchExtAbtOnTranslTableWalkLL,
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SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4,
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TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4,
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AccessFlagLL = TranslationLL + 4,
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DomainLL = AccessFlagLL + 4,
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PermissionLL = DomainLL + 4,
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DebugEvent = PermissionLL + 4,
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SynchronousExternalAbort,
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TLBConflictAbort, // Requires LPAE
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SynchPtyErrOnMemoryAccess,
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AsynchronousExternalAbort,
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AsynchPtyErrOnMemoryAccess,
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AddressSizeLL, // AArch64 only
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// Not real faults. These are faults to allow the translation function
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// to inform the memory access function not to proceed for a prefetch
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// that misses in the TLB or that targets an uncacheable address
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PrefetchTLBMiss = AddressSizeLL + 4,
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PrefetchUncacheable,
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NumFaultSources,
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FaultSourceInvalid = 0xff
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};
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/// Encodings of the fault sources when the short-desc. translation table
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/// format is in use (ARM ARM Issue C B3.13.3)
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static uint8_t shortDescFaultSources[NumFaultSources];
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/// Encodings of the fault sources when the long-desc. translation table
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/// format is in use (ARM ARM Issue C B3.13.3)
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static uint8_t longDescFaultSources[NumFaultSources];
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/// Encodings of the fault sources in AArch64 state
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static uint8_t aarch64FaultSources[NumFaultSources];
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enum AnnotationIDs
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{
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S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
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OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
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SAS, // DataAbort: Syndrome Access Size
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SSE, // DataAbort: Syndrome Sign Extend
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SRT, // DataAbort: Syndrome Register Transfer
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CM, // DataAbort: Cache Maintenance/Address Translation Op
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OFA, // DataAbort: Override fault Address. This is needed when
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// the abort is triggered by a CMO. The faulting address is
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// then the address specified in the register argument of the
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// instruction and not the cacheline address (See FAR doc)
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// AArch64 only
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SF, // DataAbort: width of the accessed register is SixtyFour
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AR // DataAbort: Acquire/Release semantics
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};
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enum TranMethod
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{
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LpaeTran,
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VmsaTran,
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UnknownTran
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};
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enum DebugType
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{
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NODEBUG = 0,
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BRKPOINT,
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VECTORCATCH,
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WPOINT_CM,
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WPOINT_NOCM
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};
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struct FaultVals
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{
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const FaultName name;
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const FaultOffset offset;
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// Offsets used for exceptions taken in AArch64 state
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const uint16_t currELTOffset;
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const uint16_t currELHOffset;
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const uint16_t lowerEL64Offset;
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const uint16_t lowerEL32Offset;
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const OperatingMode nextMode;
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const uint8_t armPcOffset;
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const uint8_t thumbPcOffset;
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// The following two values are used in place of armPcOffset and
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// thumbPcOffset when the exception return address is saved into ELR
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// registers (exceptions taken in HYP mode or in AArch64 state)
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const uint8_t armPcElrOffset;
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const uint8_t thumbPcElrOffset;
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const bool hypTrappable;
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const bool abortDisable;
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const bool fiqDisable;
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// Exception class used to appropriately set the syndrome register
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// (exceptions taken in HYP mode or in AArch64 state)
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const ExceptionClass ec;
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FaultStat count;
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FaultVals(const FaultName& name_, const FaultOffset& offset_,
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const uint16_t& currELTOffset_, const uint16_t& currELHOffset_,
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const uint16_t& lowerEL64Offset_,
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const uint16_t& lowerEL32Offset_,
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const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
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const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_,
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const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_,
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const bool& abortDisable_, const bool& fiqDisable_,
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const ExceptionClass& ec_)
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: name(name_), offset(offset_), currELTOffset(currELTOffset_),
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currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
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lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
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armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
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armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_),
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hypTrappable(hypTrappable_), abortDisable(abortDisable_),
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fiqDisable(fiqDisable_), ec(ec_) {}
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};
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ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
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machInst(_machInst), issRaw(_iss), bStep(false), from64(false),
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to64(false), fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED),
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faultUpdated(false), hypRouted(false), span(false) {}
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// Returns the actual syndrome register to use based on the target
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// exception level
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MiscRegIndex getSyndromeReg64() const;
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// Returns the actual fault address register to use based on the target
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// exception level
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MiscRegIndex getFaultAddrReg64() const;
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void invoke(ThreadContext *tc, const StaticInstPtr &inst =
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nullStaticInstPtr) override;
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void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
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nullStaticInstPtr);
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void update(ThreadContext *tc);
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bool isResetSPSR(){ return bStep; }
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bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst);
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ArmStaticInst *instrAnnotate(const StaticInstPtr &inst);
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virtual void annotate(AnnotationIDs id, uint64_t val) {}
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virtual FaultStat& countStat() = 0;
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virtual FaultOffset offset(ThreadContext *tc) = 0;
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virtual FaultOffset offset64(ThreadContext *tc) = 0;
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virtual OperatingMode nextMode() = 0;
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virtual bool routeToMonitor(ThreadContext *tc) const = 0;
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virtual bool routeToHyp(ThreadContext *tc) const { return false; }
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virtual uint8_t armPcOffset(bool isHyp) = 0;
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virtual uint8_t thumbPcOffset(bool isHyp) = 0;
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virtual uint8_t armPcElrOffset() = 0;
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virtual uint8_t thumbPcElrOffset() = 0;
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virtual bool abortDisable(ThreadContext *tc) = 0;
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virtual bool fiqDisable(ThreadContext *tc) = 0;
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virtual ExceptionClass ec(ThreadContext *tc) const = 0;
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virtual uint32_t vectorCatchFlag() const { return 0x0; }
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virtual uint32_t iss() const = 0;
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virtual bool isStage2() const { return false; }
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virtual FSR getFsr(ThreadContext *tc) const { return 0; }
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virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
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virtual bool getFaultVAddr(Addr &va) const { return false; }
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OperatingMode getToMode() const { return toMode; }
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};
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template<typename T>
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class ArmFaultVals : public ArmFault
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{
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protected:
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static FaultVals vals;
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public:
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ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
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ArmFault(_machInst, _iss) {}
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FaultName name() const override { return vals.name; }
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FaultStat & countStat() override { return vals.count; }
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FaultOffset offset(ThreadContext *tc) override;
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FaultOffset offset64(ThreadContext *tc) override;
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OperatingMode nextMode() override { return vals.nextMode; }
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virtual bool routeToMonitor(ThreadContext *tc) const override {
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return false;
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}
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uint8_t armPcOffset(bool isHyp) override {
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return isHyp ? vals.armPcElrOffset
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: vals.armPcOffset;
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}
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uint8_t thumbPcOffset(bool isHyp) override {
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return isHyp ? vals.thumbPcElrOffset
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: vals.thumbPcOffset;
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}
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uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
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uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
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bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; }
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bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
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ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
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uint32_t iss() const override { return issRaw; }
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};
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class Reset : public ArmFaultVals<Reset>
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{
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protected:
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Addr getVector(ThreadContext *tc) override;
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public:
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void invoke(ThreadContext *tc, const StaticInstPtr &inst =
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nullStaticInstPtr) override;
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};
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class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
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{
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protected:
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bool unknown;
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bool disabled;
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ExceptionClass overrideEc;
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const char *mnemonic;
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public:
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UndefinedInstruction(ExtMachInst _machInst,
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bool _unknown,
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const char *_mnemonic = NULL,
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bool _disabled = false) :
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ArmFaultVals<UndefinedInstruction>(_machInst),
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unknown(_unknown), disabled(_disabled),
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overrideEc(EC_INVALID), mnemonic(_mnemonic)
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{}
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UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
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ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
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ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
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unknown(false), disabled(true), overrideEc(_overrideEc),
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mnemonic(_mnemonic)
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{}
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void invoke(ThreadContext *tc, const StaticInstPtr &inst =
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nullStaticInstPtr) override;
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bool routeToHyp(ThreadContext *tc) const override;
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ExceptionClass ec(ThreadContext *tc) const override;
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uint32_t iss() const override;
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uint32_t vectorCatchFlag() const override { return 0x02000002; }
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};
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class SupervisorCall : public ArmFaultVals<SupervisorCall>
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{
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protected:
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ExceptionClass overrideEc;
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public:
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SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
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ExceptionClass _overrideEc = EC_INVALID) :
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ArmFaultVals<SupervisorCall>(_machInst, _iss),
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overrideEc(_overrideEc)
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{
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bStep = true;
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}
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void invoke(ThreadContext *tc, const StaticInstPtr &inst =
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nullStaticInstPtr) override;
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bool routeToHyp(ThreadContext *tc) const override;
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ExceptionClass ec(ThreadContext *tc) const override;
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uint32_t iss() const override;
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uint32_t vectorCatchFlag() const override { return 0x04000404; }
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};
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class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
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{
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public:
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SecureMonitorCall(ExtMachInst _machInst) :
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ArmFaultVals<SecureMonitorCall>(_machInst)
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{
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bStep = true;
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}
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void invoke(ThreadContext *tc, const StaticInstPtr &inst =
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nullStaticInstPtr) override;
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ExceptionClass ec(ThreadContext *tc) const override;
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uint32_t iss() const override;
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uint32_t vectorCatchFlag() const override { return 0x00000400; }
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};
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class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
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{
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protected:
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ExtMachInst machInst;
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ExceptionClass overrideEc;
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public:
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SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
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ExceptionClass _overrideEc = EC_INVALID) :
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ArmFaultVals<SupervisorTrap>(_machInst, _iss),
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overrideEc(_overrideEc)
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{}
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bool routeToHyp(ThreadContext *tc) const override;
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uint32_t iss() const override;
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ExceptionClass ec(ThreadContext *tc) const override;
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};
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class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
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{
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protected:
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ExtMachInst machInst;
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ExceptionClass overrideEc;
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public:
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SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
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ExceptionClass _overrideEc = EC_INVALID) :
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ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
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overrideEc(_overrideEc)
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{}
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ExceptionClass ec(ThreadContext *tc) const override;
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};
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class HypervisorCall : public ArmFaultVals<HypervisorCall>
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{
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public:
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HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
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bool routeToHyp(ThreadContext *tc) const override;
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bool routeToMonitor(ThreadContext *tc) const override;
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ExceptionClass ec(ThreadContext *tc) const override;
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uint32_t vectorCatchFlag() const override { return 0xFFFFFFFF; }
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};
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class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
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{
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protected:
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ExtMachInst machInst;
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ExceptionClass overrideEc;
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public:
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HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
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ExceptionClass _overrideEc = EC_INVALID) :
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ArmFaultVals<HypervisorTrap>(_machInst, _iss),
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overrideEc(_overrideEc)
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{}
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ExceptionClass ec(ThreadContext *tc) const override;
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};
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template <class T>
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class AbortFault : public ArmFaultVals<T>
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{
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protected:
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/**
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* The virtual address the fault occured at. If 2 stages of
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* translation are being used then this is the intermediate
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* physical address that is the starting point for the second
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* stage of translation.
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*/
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Addr faultAddr;
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/**
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* Original virtual address. If the fault was generated on the
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* second stage of translation then this variable stores the
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* virtual address used in the original stage 1 translation.
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*/
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Addr OVAddr;
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bool write;
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TlbEntry::DomainType domain;
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uint8_t source;
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uint8_t srcEncoded;
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bool stage2;
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bool s1ptw;
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ArmFault::TranMethod tranMethod;
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ArmFault::DebugType debug;
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public:
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AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
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uint8_t _source, bool _stage2,
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ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran,
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ArmFault::DebugType _debug = ArmFault::NODEBUG) :
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faultAddr(_faultAddr), OVAddr(0), write(_write),
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domain(_domain), source(_source), srcEncoded(0),
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stage2(_stage2), s1ptw(false), tranMethod(_tranMethod), debug(_debug)
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{}
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bool getFaultVAddr(Addr &va) const override;
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void invoke(ThreadContext *tc, const StaticInstPtr &inst =
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nullStaticInstPtr) override;
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FSR getFsr(ThreadContext *tc) const override;
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uint8_t getFaultStatusCode(ThreadContext *tc) const;
|
|
bool abortDisable(ThreadContext *tc) override;
|
|
uint32_t iss() const override;
|
|
bool isStage2() const override { return stage2; }
|
|
void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
|
|
void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override;
|
|
bool isMMUFault() const;
|
|
};
|
|
|
|
class PrefetchAbort : public AbortFault<PrefetchAbort>
|
|
{
|
|
public:
|
|
static const MiscRegIndex FsrIndex = MISCREG_IFSR;
|
|
static const MiscRegIndex FarIndex = MISCREG_IFAR;
|
|
static const MiscRegIndex HFarIndex = MISCREG_HIFAR;
|
|
|
|
PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
|
|
ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran,
|
|
ArmFault::DebugType _debug = ArmFault::NODEBUG) :
|
|
AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
|
|
_source, _stage2, _tranMethod, _debug)
|
|
{}
|
|
|
|
ExceptionClass ec(ThreadContext *tc) const override;
|
|
// @todo: external aborts should be routed if SCR.EA == 1
|
|
bool routeToMonitor(ThreadContext *tc) const override;
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
uint32_t vectorCatchFlag() const override { return 0x08000808; }
|
|
};
|
|
|
|
class DataAbort : public AbortFault<DataAbort>
|
|
{
|
|
public:
|
|
static const MiscRegIndex FsrIndex = MISCREG_DFSR;
|
|
static const MiscRegIndex FarIndex = MISCREG_DFAR;
|
|
static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
|
|
bool isv;
|
|
uint8_t sas;
|
|
uint8_t sse;
|
|
uint8_t srt;
|
|
uint8_t cm;
|
|
|
|
// AArch64 only
|
|
bool sf;
|
|
bool ar;
|
|
|
|
DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
|
|
bool _stage2=false,
|
|
ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran,
|
|
ArmFault::DebugType _debug_type=ArmFault::NODEBUG) :
|
|
AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
|
|
_tranMethod, _debug_type),
|
|
isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false)
|
|
{}
|
|
|
|
ExceptionClass ec(ThreadContext *tc) const override;
|
|
// @todo: external aborts should be routed if SCR.EA == 1
|
|
bool routeToMonitor(ThreadContext *tc) const override;
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
uint32_t iss() const override;
|
|
void annotate(AnnotationIDs id, uint64_t val) override;
|
|
uint32_t vectorCatchFlag() const override { return 0x10001010; }
|
|
};
|
|
|
|
class VirtualDataAbort : public AbortFault<VirtualDataAbort>
|
|
{
|
|
public:
|
|
static const MiscRegIndex FsrIndex = MISCREG_DFSR;
|
|
static const MiscRegIndex FarIndex = MISCREG_DFAR;
|
|
static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
|
|
|
|
VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
|
|
uint8_t _source) :
|
|
AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
|
|
{}
|
|
|
|
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
|
|
};
|
|
|
|
class Interrupt : public ArmFaultVals<Interrupt>
|
|
{
|
|
public:
|
|
bool routeToMonitor(ThreadContext *tc) const override;
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
bool abortDisable(ThreadContext *tc) override;
|
|
uint32_t vectorCatchFlag() const override { return 0x40004040; }
|
|
};
|
|
|
|
class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
|
|
{
|
|
public:
|
|
VirtualInterrupt();
|
|
};
|
|
|
|
class FastInterrupt : public ArmFaultVals<FastInterrupt>
|
|
{
|
|
public:
|
|
bool routeToMonitor(ThreadContext *tc) const override;
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
bool abortDisable(ThreadContext *tc) override;
|
|
bool fiqDisable(ThreadContext *tc) override;
|
|
uint32_t vectorCatchFlag() const override { return 0x80008080; }
|
|
};
|
|
|
|
class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
|
|
{
|
|
public:
|
|
VirtualFastInterrupt();
|
|
};
|
|
|
|
/// PC alignment fault (AArch64 only)
|
|
class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
|
|
{
|
|
protected:
|
|
/// The unaligned value of the PC
|
|
Addr faultPC;
|
|
public:
|
|
PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
|
|
{}
|
|
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
|
|
nullStaticInstPtr) override;
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
};
|
|
|
|
/// Stack pointer alignment fault (AArch64 only)
|
|
class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
|
|
{
|
|
public:
|
|
SPAlignmentFault();
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
};
|
|
|
|
/// System error (AArch64 only)
|
|
class SystemError : public ArmFaultVals<SystemError>
|
|
{
|
|
public:
|
|
SystemError();
|
|
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
|
|
nullStaticInstPtr) override;
|
|
bool routeToMonitor(ThreadContext *tc) const override;
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
};
|
|
|
|
/// System error (AArch64 only)
|
|
class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
|
|
{
|
|
public:
|
|
SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss);
|
|
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
ExceptionClass ec(ThreadContext *tc) const override;
|
|
};
|
|
|
|
class HardwareBreakpoint : public ArmFaultVals<HardwareBreakpoint>
|
|
{
|
|
private:
|
|
Addr vAddr;
|
|
public:
|
|
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
|
|
nullStaticInstPtr) override;
|
|
HardwareBreakpoint(Addr _vaddr, uint32_t _iss);
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
ExceptionClass ec(ThreadContext *tc) const override;
|
|
};
|
|
|
|
class Watchpoint : public ArmFaultVals<Watchpoint>
|
|
{
|
|
private:
|
|
Addr vAddr;
|
|
bool write;
|
|
bool cm;
|
|
|
|
public:
|
|
Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm);
|
|
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
|
|
nullStaticInstPtr) override;
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
uint32_t iss() const override;
|
|
ExceptionClass ec(ThreadContext *tc) const override;
|
|
void annotate(AnnotationIDs id, uint64_t val) override;
|
|
};
|
|
|
|
class SoftwareStepFault : public ArmFaultVals<SoftwareStepFault>
|
|
{
|
|
private:
|
|
bool isldx;
|
|
bool stepped;
|
|
|
|
public:
|
|
SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx, bool stepped);
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
uint32_t iss() const override;
|
|
ExceptionClass ec(ThreadContext *tc) const override;
|
|
};
|
|
|
|
// A fault that flushes the pipe, excluding the faulting instructions
|
|
class ArmSev : public ArmFaultVals<ArmSev>
|
|
{
|
|
public:
|
|
ArmSev () {}
|
|
void invoke(ThreadContext *tc, const StaticInstPtr &inst =
|
|
nullStaticInstPtr) override;
|
|
};
|
|
|
|
/// Illegal Instruction Set State fault (AArch64 only)
|
|
class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
|
|
{
|
|
public:
|
|
IllegalInstSetStateFault();
|
|
|
|
bool routeToHyp(ThreadContext *tc) const override;
|
|
};
|
|
|
|
/*
|
|
* Explicitly declare template static member variables to avoid warnings
|
|
* in some clang versions
|
|
*/
|
|
template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<HardwareBreakpoint>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<Watchpoint>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<SoftwareStepFault>::vals;
|
|
template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals;
|
|
|
|
/**
|
|
* Returns true if the fault passed as a first argument was triggered
|
|
* by a memory access, false otherwise.
|
|
* If true it is storing the faulting address in the va argument
|
|
*
|
|
* @param fault generated fault
|
|
* @param va function will modify this passed-by-reference parameter
|
|
* with the correct faulting virtual address
|
|
* @return true if va contains a valid value, false otherwise
|
|
*/
|
|
bool getFaultVAddr(Fault fault, Addr &va);
|
|
|
|
|
|
} // namespace ArmISA
|
|
|
|
#endif // __ARM_FAULTS_HH__
|