Chuan Zhu 8dabce896a arch-arm: Fix masking in CPACR_EL1 ...

Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit
CPACR_EL1[31] is RES0 but should be made stateful, since it allows
programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1
is removed.

Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10046
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2018-04-18 15:23:07 +00:00

..

arch

arch-arm: Fix masking in CPACR_EL1

2018-04-18 15:23:07 +00:00

base

base: Make bitunion output functions static/inline.

2018-03-30 19:22:46 +00:00

cpu

cpu: Remove ExtMachInst typedefs from the O3 CPU model.

2018-03-27 10:58:01 +00:00

dev

dev, arm: Cleanup Pl050 interrupt handling

2018-04-18 09:14:02 +00:00

doc

sim: Adding support for power models

2016-06-06 17:16:44 +01:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

gpu-compute: fix bad asserts in gpu tlb and cu tlb port

2018-04-17 22:50:37 +00:00

kern

sim-se: Add /sys/devices/system/cpu/online file

2018-03-15 20:45:34 +00:00

learning_gem5

learning_gem5: Add a simple Ruby protocol

2018-03-23 15:50:28 +00:00

mem

mem-cache: Revamp multiple size tracking for FALRU caches

2018-04-18 13:37:48 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

sim

sim-se: Fix fallthrough in prlimit

2018-03-15 20:45:34 +00:00

unittest

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00