0f33b2c1d5
Add a memory system component that delays traffic. The base functionality to delay packets is implemented in the abstract MemDelay class. This class exposes three methods that control packet delays: * delayReq(pkt) * delayResp(pkt) * delaySnoopResp(pkt) These methods should be specialized to implement delays for specific packet types. The class SimpleMemDelay uses the MemDelay base class to implement constant delays for read/write requests and responses. The intention is that these classes can be used for rapid prototyping of components that add a small fixed delay and the same throughput as the interconnect. I.e., any buffering done in the base class will be small and proportional to the introduced delay. Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11521 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
58 lines
2.6 KiB
Python
58 lines
2.6 KiB
Python
# Copyright (c) 2018 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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from m5.params import *
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from MemObject import MemObject
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class MemDelay(MemObject):
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type = 'MemDelay'
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cxx_header = 'mem/mem_delay.hh'
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abstract = True
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master = MasterPort("Master port")
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slave = SlavePort("Slave port")
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class SimpleMemDelay(MemDelay):
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type = 'SimpleMemDelay'
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cxx_header = 'mem/mem_delay.hh'
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read_req = Param.Latency("0t", "Read request delay")
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read_resp = Param.Latency("0t", "Read response delay")
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write_req = Param.Latency("0t", "Write request delay")
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write_resp = Param.Latency("0t", "Write response delay")
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