Files
gem5/util/cpt_upgraders/x86-add-xcr0.py
Matthew Poremba c495ff84ec util: Make x86-add-xcr0 work for testlib checkpoints
Change-Id: I7b93d7afc7710bd43412a77a204ce8838d0bfb4e
2024-04-29 11:45:55 -07:00

55 lines
2.3 KiB
Python

# Copyright (c) 2024 Advanced Micro Devices, Inc.
# All rights reserved.
#
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# 1. Redistributions of source code must retain the above copyright notice,
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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def upgrader(cpt):
"""
Update the checkpoint to include the XCR0 register if X86 checkpoint.
The value is set to the default of 1.
"""
import re
for sec in cpt.sections():
if re.search(r".*sys.*\.cpu.*\.isa$", sec):
if cpt.get(sec, "isaName") == "x86":
regVals = cpt.get(sec, "regVal")
# Add the default value of XCR0 (1) if missing
regVals = f"{regVals} 1"
cpt.set(sec, "regVal", regVals)
elif re.search(rf"board\.processor\.cores.*isa$", sec):
# ISA name doesn't appear to be anywhere in the checkpoint.
# Assume it is X86.
regVals = cpt.get(sec, "regVal")
# Add the default value of XCR0 (1) if missing
regVals = f"{regVals} 1"
cpt.set(sec, "regVal", regVals)