Giacomo Travaglini 854662f48f arch-arm: Check OSH domain as well for cacheability attribute ...

Make table walks uncacheable if marked as uncacheable
in either inner or outer shareable domain

Change-Id: I5898a3b91b5b919e0beda6c6fe896394e3ab94df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2024-05-29 09:30:58 +01:00

..

arch

arch-arm: Check OSH domain as well for cacheability attribute

2024-05-29 09:30:58 +01:00

base

misc: Add a generic cache library

2024-04-10 16:17:57 -04:00

cpu

Revert "cpu-kvm: Support perf counters on hybrid host architectures" (#1127)

2024-05-21 08:14:10 -07:00

dev

dev: add reset wrap mode to mouse.cc (#1149)

2024-05-21 10:55:03 -07:00

doc

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doxygen

…

gpu-compute

arch-vega: Architected flat scratch and scratch insts

2024-05-16 09:23:03 -07:00

kern

misc: Fix 'maybe-uninitialized' warn turn off (#706)

2023-12-21 18:45:56 -08:00

learning_gem5

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mem

mem-ruby: Remove VIPER StoreThrough temp cache storage (#1156)

2024-05-28 11:02:00 -07:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

stdlib: change default exit event for SIMPOINT_BEGIN (#1085)

2024-05-13 14:11:00 -07:00

sim

arch-riscv: Add support for RISC-V semihosting (#681)

2024-04-27 05:12:32 -07:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: remove if clause in Gem5ToTlmBridgeBase (#1059)

2024-04-25 11:15:30 -07:00

test_objects

scons,tests: Add 'USE_TEST_OBJECTS' kconfig

2024-04-04 13:04:21 -07:00

Doxyfile

misc: Change version information to develop for v24.0

2023-12-27 12:29:52 -08:00

Kconfig

scons,tests: Add 'USE_TEST_OBJECTS' kconfig

2024-04-04 13:04:21 -07:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00