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arch-arm: Check OSH domain as well for cacheability attribute

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Make table walks uncacheable if marked as uncacheable
in either inner or outer shareable domain

Change-Id: I5898a3b91b5b919e0beda6c6fe896394e3ab94df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-02-22 15:23:37 +00:00
parent 4acc20dac1
commit 854662f48f
1 changed files with 12 additions and 6 deletions
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18
src/arch/arm/table_walker.cc
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@@ -898,7 +898,8 @@ TableWalker::processWalkAArch64()
tg = GrainMap_tg0[currState->vtcr.tg0];
ps = currState->vtcr.ps;
currState->isUncacheable = currState->vtcr.irgn0 == 0;
currState->isUncacheable = currState->vtcr.irgn0 == 0 ||
currState->vtcr.orgn0 == 0;
} else {
switch (bits(currState->vaddr, top_bit)) {
case 0:
@@ -907,7 +908,8 @@ TableWalker::processWalkAArch64()
tsz = 64 - currState->tcr.t0sz;
tg = GrainMap_tg0[currState->tcr.tg0];
currState->hpd = currState->tcr.hpd0;
currState->isUncacheable = currState->tcr.irgn0 == 0;
currState->isUncacheable = currState->tcr.irgn0 == 0 ||
currState->tcr.orgn0 == 0;
vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
top_bit, tg, tsz, true);
@@ -920,7 +922,8 @@ TableWalker::processWalkAArch64()
tsz = 64 - currState->tcr.t1sz;
tg = GrainMap_tg1[currState->tcr.tg1];
currState->hpd = currState->tcr.hpd1;
currState->isUncacheable = currState->tcr.irgn1 == 0;
currState->isUncacheable = currState->tcr.irgn1 == 0 ||
currState->tcr.orgn1 == 0;
vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
top_bit, tg, tsz, false);
@@ -944,7 +947,8 @@ TableWalker::processWalkAArch64()
tg = GrainMap_tg0[currState->tcr.tg0];
currState->hpd = currState->hcr.e2h ?
currState->tcr.hpd0 : currState->tcr.hpd;
currState->isUncacheable = currState->tcr.irgn0 == 0;
currState->isUncacheable = currState->tcr.irgn0 == 0 ||
currState->tcr.orgn0 == 0;
vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
top_bit, tg, tsz, true);
@@ -958,7 +962,8 @@ TableWalker::processWalkAArch64()
tsz = 64 - currState->tcr.t1sz;
tg = GrainMap_tg1[currState->tcr.tg1];
currState->hpd = currState->tcr.hpd1;
currState->isUncacheable = currState->tcr.irgn1 == 0;
currState->isUncacheable = currState->tcr.irgn1 == 0 ||
currState->tcr.orgn1 == 0;
vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
top_bit, tg, tsz, false);
@@ -980,7 +985,8 @@ TableWalker::processWalkAArch64()
tsz = 64 - currState->tcr.t0sz;
tg = GrainMap_tg0[currState->tcr.tg0];
currState->hpd = currState->tcr.hpd;
currState->isUncacheable = currState->tcr.irgn0 == 0;
currState->isUncacheable = currState->tcr.irgn0 == 0 ||
currState->tcr.orgn0 == 0;
vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
top_bit, tg, tsz, true);