Giacomo Travaglini 81d3c6307d arch-arm: add Sve mla and mls indexed (#596) ...

This contains the implementation of mla and MLS index version
instructions from ARM SVE2 ISA specification.

2023-12-07 21:47:35 +00:00

..

arch

arch-arm: add Sve mla and mls indexed (#596)

2023-12-07 21:47:35 +00:00

base

base: Add a size field to the Symbol object

2023-12-01 22:00:35 +00:00

cpu

arch-arm: Only build ArmCapstoneDisassembler when ISA is arm (#553)

2023-12-03 13:22:11 -08:00

dev

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

doc

…

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

kern

Fix for gem5 Issue #550 (#636)

2023-12-01 18:06:20 -08:00

learning_gem5

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mem

mem-ruby: Fix compile error in chi-dvm-funcs (#646)

2023-12-03 13:39:26 -08:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

stdlib: Add Kernel Panic/Oops exit event to stdlib

2023-12-04 16:52:14 -08:00

sim

Fix for gem5 Issue #550 (#636)

2023-12-01 18:06:20 -08:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: Bugfix in TlmToGem5Bridge (#615)

2023-12-01 16:18:51 -08:00

Doxyfile

misc: Update version info for develop branch

2023-07-10 12:28:44 -07:00

Kconfig

scons: Add new config option HAVE_CAPSTONE to Kconfig

2023-11-23 08:26:11 +08:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00