Gabe Black 818f3ae22f SPARC compiles for SE! ...

arch/sparc/isa/decoder.isa:
    Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
    Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
    Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
    Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
    Changed regSpace to have the correct size.
arch/sparc/utility.hh:
    A new file for sparc to match the one for alpha.

--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932

2006-03-28 19:36:34 -05:00

..

alpha

Merge m5.eecs.umich.edu:/bk/newmem

2006-03-16 14:08:31 -05:00

mips

support for unaligned memory access

2006-03-19 13:40:03 -05:00

sparc

SPARC compiles for SE!

2006-03-28 19:36:34 -05:00

isa_parser.py

Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.

2006-03-14 15:55:00 -05:00

isa_specific.hh

Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu

2006-03-14 18:28:51 -05:00

SConscript

Moved registerfile.hh to regfile.hh

2006-03-14 16:05:44 -05:00