Andrea Mondelli 96cc03f90d mem-cache: alias to mem::getMasterPort in TLB class ...

TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().

The TLB::getMasterPort() is renamed according to the expected behavior.

Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2019-03-01 16:46:47 +00:00

..

freebsd

arch, base, dev, kern, sym: FreeBSD support

2015-04-29 22:35:23 -05:00

linux

arm,sim: fix context switch stats dumps for ARM64/Linux

2017-06-22 13:32:04 +00:00

BaseTLB.py

python: Enforce absolute imports for Python 3 compatibility

2019-02-23 23:34:05 +00:00

debugfaults.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

decode_cache.cc

arch: cpu: Make the ExtMachInst type a template argument in InstMap.

2018-03-27 10:57:54 +00:00

decode_cache.hh

arch: cpu: Make the ExtMachInst type a template argument in InstMap.

2018-03-27 10:57:54 +00:00

ISACommon.py

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

locked_mem.hh

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

memhelpers.hh

arch: Explicitly specify the endianness in the generic mem helpers.

2018-10-12 23:58:58 +00:00

mmapped_ipr.cc

arch: Include some additional headers in arch/generic/mmapped_ipr.cc.

2018-10-17 20:19:03 +00:00

mmapped_ipr.hh

mem: Use a flag instead of address bit 63 for generic IPRs

2013-10-15 13:24:35 +02:00

pseudo_inst.cc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

pseudo_inst.hh

kvm, x86: Adding support for SE mode execution

2014-11-23 18:01:08 -08:00

SConscript

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

tlb.cc

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

tlb.hh

mem-cache: alias to mem::getMasterPort in TLB class

2019-03-01 16:46:47 +00:00

traits.hh

cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

2019-01-25 12:55:27 +00:00

types.hh

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

vec_pred_reg.hh

arch,cpu: Add vector predicate registers

2019-01-30 16:57:54 +00:00

vec_reg.hh

arch,cpu: Add vector predicate registers

2019-01-30 16:57:54 +00:00