Giacomo Travaglini 7d5d1cd9c8 dev-arm: Rewrite SMMUEvent ...

The struct fields of the SMMUEvent were not matching the SMMUv3 specs.
This was "not an issue" as events have been implicitly disabled until
now (every translation error was aborting simulation)

With generateEvent we automatically construct a SMMU event from
a translation result.

Change-Id: Iba6a08d551c0a99bb58c4118992f1d2b683f62cf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2024-03-08 11:29:22 +00:00

..

amdgpu

dev-amdgpu: Limit SDMA NOP count to wptr boundary (#806)

2024-01-25 15:35:35 -08:00

arm

dev-arm: Rewrite SMMUEvent

2024-03-08 11:29:22 +00:00

hsa

misc: Remove all references to GCN3

2024-01-17 11:11:06 -06:00

i2c

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

lupio

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mips

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

net

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

pci

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

ps2

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

qemu

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

riscv

arch-riscv,dev: Update the PLIC implementation (#886)

2024-02-26 10:32:53 -08:00

serial

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

sparc

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

storage

dev: Fix off-by-one in IDE controller PCI register allocation (#824)

2024-02-01 10:14:28 -08:00

virtio

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

x86

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

baddev.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

baddev.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

BadDevice.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

Device.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

dma_device.cc

dev: Warn when resp packet is error in dma port

2023-07-07 07:12:54 +00:00

dma_device.hh

cpu,mem,dev: Use Addr for cacheLineSize

2023-09-20 14:16:46 -07:00

dma_virt_device.cc

misc: Remove AMD license addition

2021-12-11 04:00:56 +00:00

dma_virt_device.hh

misc: Remove AMD license addition

2021-12-11 04:00:56 +00:00

intel_8254_timer.cc

dev: Refactor how counters are set up in the 8254 timer.

2022-01-16 03:43:58 +00:00

intel_8254_timer.hh

dev: Refactor how counters are set up in the 8254 timer.

2022-01-16 03:43:58 +00:00

intpin.hh

fastmodel,dev: Rework the Int*Pin classes with Signal*Port.

2022-12-16 07:19:05 +00:00

IntPin.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

io_device.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

io_device.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

isa_fake.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

isa_fake.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

mc146818.cc

dev: Ignore MC146818 UIP bit / Fix x86 Linux 5.11+ boot

2023-01-17 16:43:10 +00:00

mc146818.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

pixelpump.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

pixelpump.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

platform.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

platform.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

Platform.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

reg_bank.hh

dev: RegisterBank addRegistersAt for fragmented reg banks (#902)

2024-03-01 15:32:40 +00:00

reg_bank.test.cc

dev: RegisterBank addRegistersAt for fragmented reg banks (#902)

2024-03-01 15:32:40 +00:00

ResetPort.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

rtcreg.h

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

SConscript

dev: add debug flag in register bank. (#386)

2023-11-15 10:04:46 -08:00