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Srikant Bharadwaj 6fa7e50d66 mem-garnet: Enable bridge rescheduling for DVFS 
The Bridge SimObject, which hosts the CDC and SerDes functionality,
could be woken up out-of-order when changing frequencies in DVFS.
This change ensures there is no packet drop during the transition
times.

Change-Id: I40240dcb3e957217abd2d7ad22cc4f78809f7b49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44287
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 18:04:42 +00:00
..
arch
arch-arm: Make TLB misses from a sw prefetch visible
2021-04-14 15:50:22 +00:00
base
scons: Convert gem5_scons.Configure to a context manager.
2021-04-13 01:04:54 +00:00
cpu
cpu-o3: Fix missing overrides
2021-04-14 00:09:06 +00:00
dev
scons: Convert gem5_scons.Configure to a context manager.
2021-04-13 01:04:54 +00:00
doc
misc: Removed unneeded Doxygen pages
2020-04-25 01:08:38 +00:00
doxygen
base,misc: Add group definitions for newly tagged API in src/base
2020-09-08 22:29:43 +00:00
gpu-compute
arch,cpu,gpu-compute: Further simplify VecRegContainer.
2021-04-10 07:31:23 +00:00
kern
misc: Fix remaining opening braces
2021-04-07 01:29:31 +00:00
learning_gem5
scons: Pull domain specific build setup out of SConstruct.
2021-04-03 01:18:17 +00:00
mem
mem-garnet: Enable bridge rescheduling for DVFS
2021-04-14 18:04:42 +00:00
proto
scons: Convert gem5_scons.Configure to a context manager.
2021-04-13 01:04:54 +00:00
python
python: Don't try setting the parent of null SimObject pointers.
2021-04-11 22:16:52 +00:00
sim
scons: Convert gem5_scons.Configure to a context manager.
2021-04-13 01:04:54 +00:00
systemc
systemc: Fix tlm phase ordering in Gem5ToTlmBridge
2021-04-14 16:46:59 +00:00
unittest
misc: Fix coding style for class-opening braces
2021-03-19 20:57:24 +00:00
Doxyfile
misc: Update version to "DEVELOP-FOR-V21.1"
2021-03-26 18:21:34 +00:00
SConscript
scons,python: Always generate default create() methods.
2021-03-11 22:54:05 +00:00