c498d8bced
The BaseCPU type had been specializing itself based on the value of TARGET_ISA, which is not compatible with building more than one ISA at a time. This change refactors the CPU models so that the BaseCPU is more general, and the ISA specific components are added to the CPU when the CPU types are fully specialized. For instance, The AtomicSimpleCPU has a version called X86AtomicSimpleCPU which installs the X86 specific aspects of the CPU. This specialization is done in three ways. 1. The mmu parameter is assigned an instance of the architecture specific MMU type. This provides a reasonable default, but also avoids having having to use the ISA specific type when the parameter is created. 2. The ISA specific types are made available as class attributes, and the utility functions (including __init__!) in the BaseCPU class can refer to them to get the types they need to set up the CPU at run time. Because SimObjects have strange, unhelpful semantics as far as assigning to their attributes, these types need to be set up in a non-SimObject class, which is then brought in as a base of the actual SimObject type. Because the metaclass of this other type is just "type", things work like you would expect. The SimObject doesn't do any special processing of base classes if they aren't also SimObjects, so these attributes survive and are accessible using normal lookup in the BaseCPU class. 3. There are some methods like addCheckerCPU and properties like needsTSO which have ISA specific values or behaviors. These are set in the ISA specific subclass, where they are inherently specific to an ISA and don't need to check TARGET_ISA. Also, the DummyChecker which was set up for the BaseSimpleCPU which doesn't actually do anything in either C++ or python was not carried forward. The CPU type still exists, but it isn't installed in the simple CPUs. To provide backward compatibility, each ISA implements a .py file which matches the original .py for a CPU, and the original is renamed with a Base prefix. The ISA specific version creates an alias with the old CPU name which maps to the ISA specific type. This way, old scripts which refer to, for example, AtomicSimpleCPU, will get the X86AtomicSimpleCPU if the x86 version was compiled in, the ArmAtomicSimpleCPU on arm, etc. Unfortunately, because of how tags on PySource and by extension SimObjects are implemented right now, if you set the tags on two SimObjects or PySources which have the same module path, the later will overwrite the former whether or not they both would be included. There are some changes in review which would revamp this and make it work like you would expect, without this central bookkeeping which has the conflict. Since I can't use that here, I fell back to checking TARGET_ISA to decide whether to tell SCons about those files at all. In the long term, this mechanism should be revamped so that these compatibility types are only available if there is exactly one ISA compiled into gem5. After the configs have been updated and no longer assume they can use AtomicSimpleCPU in all cases, then these types can be deleted. Also, because ISAs can now either provide subclasses for a CPU or not, the CPU_MODELS variable has been removed, meaning the non-ISA specialized versions of those CPU models will always be included in gem5, except when building the NULL ISA. In the future, a more granular config mechanism will hopefully be implemented for *all* of gem5 and not just the CPUs, and these can be conditional again in case you only need certain models, and want to reduce build time or binary size by excluding the others. Change-Id: I02fc3f645c551678ede46268bbea9f66c3f6c74b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52490 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
570 lines
19 KiB
C++
570 lines
19 KiB
C++
/*
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* Copyright (c) 2011-2012, 2014 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_INST_QUEUE_HH__
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#define __CPU_O3_INST_QUEUE_HH__
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#include <list>
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#include <map>
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#include <queue>
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#include <vector>
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#include "base/statistics.hh"
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#include "base/types.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/dep_graph.hh"
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#include "cpu/o3/dyn_inst_ptr.hh"
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#include "cpu/o3/limits.hh"
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#include "cpu/o3/mem_dep_unit.hh"
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#include "cpu/o3/store_set.hh"
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#include "cpu/op_class.hh"
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#include "cpu/timebuf.hh"
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#include "enums/SMTQueuePolicy.hh"
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#include "sim/eventq.hh"
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namespace gem5
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{
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struct BaseO3CPUParams;
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namespace memory
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{
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class MemInterface;
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} // namespace memory
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namespace o3
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{
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class FUPool;
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class CPU;
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class IEW;
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/**
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* A standard instruction queue class. It holds ready instructions, in
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* order, in seperate priority queues to facilitate the scheduling of
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* instructions. The IQ uses a separate linked list to track dependencies.
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* Similar to the rename map and the free list, it expects that
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* floating point registers have their indices start after the integer
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* registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
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* and 96-191 are fp). This remains true even for both logical and
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* physical register indices. The IQ depends on the memory dependence unit to
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* track when memory operations are ready in terms of ordering; register
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* dependencies are tracked normally. Right now the IQ also handles the
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* execution timing; this is mainly to allow back-to-back scheduling without
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* requiring IEW to be able to peek into the IQ. At the end of the execution
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* latency, the instruction is put into the queue to execute, where it will
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* have the execute() function called on it.
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* @todo: Make IQ able to handle multiple FU pools.
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*/
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class InstructionQueue
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{
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public:
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// Typedef of iterator through the list of instructions.
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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/** FU completion event class. */
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class FUCompletion : public Event
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{
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private:
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/** Executing instruction. */
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DynInstPtr inst;
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/** Index of the FU used for executing. */
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int fuIdx;
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/** Pointer back to the instruction queue. */
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InstructionQueue *iqPtr;
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/** Should the FU be added to the list to be freed upon
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* completing this event.
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*/
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bool freeFU;
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public:
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/** Construct a FU completion event. */
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FUCompletion(const DynInstPtr &_inst, int fu_idx,
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InstructionQueue *iq_ptr);
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virtual void process();
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virtual const char *description() const;
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void setFreeFU() { freeFU = true; }
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};
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/** Constructs an IQ. */
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InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr,
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const BaseO3CPUParams ¶ms);
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/** Destructs the IQ. */
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~InstructionQueue();
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/** Returns the name of the IQ. */
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std::string name() const;
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/** Resets all instruction queue state. */
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void resetState();
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/** Sets active threads list. */
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void setActiveThreads(std::list<ThreadID> *at_ptr);
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/** Sets the timer buffer between issue and execute. */
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void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
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/** Sets the global time buffer. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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/** Determine if we are drained. */
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bool isDrained() const;
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/** Perform sanity checks after a drain. */
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void drainSanityCheck() const;
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/** Takes over execution from another CPU's thread. */
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void takeOverFrom();
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/** Number of entries needed for given amount of threads. */
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int entryAmount(ThreadID num_threads);
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/** Resets max entries for all threads. */
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void resetEntries();
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/** Returns total number of free entries. */
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unsigned numFreeEntries();
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/** Returns number of free entries for a thread. */
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unsigned numFreeEntries(ThreadID tid);
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/** Returns whether or not the IQ is full. */
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bool isFull();
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/** Returns whether or not the IQ is full for a specific thread. */
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bool isFull(ThreadID tid);
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/** Returns if there are any ready instructions in the IQ. */
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bool hasReadyInsts();
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/** Inserts a new instruction into the IQ. */
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void insert(const DynInstPtr &new_inst);
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/** Inserts a new, non-speculative instruction into the IQ. */
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void insertNonSpec(const DynInstPtr &new_inst);
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/** Inserts a memory or write barrier into the IQ to make sure
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* loads and stores are ordered properly.
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*/
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void insertBarrier(const DynInstPtr &barr_inst);
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/** Returns the oldest scheduled instruction, and removes it from
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* the list of instructions waiting to execute.
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*/
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DynInstPtr getInstToExecute();
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/** Gets a memory instruction that was referred due to a delayed DTB
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* translation if it is now ready to execute. NULL if none available.
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*/
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DynInstPtr getDeferredMemInstToExecute();
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/** Gets a memory instruction that was blocked on the cache. NULL if none
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* available.
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*/
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DynInstPtr getBlockedMemInstToExecute();
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/**
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* Records the instruction as the producer of a register without
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* adding it to the rest of the IQ.
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*/
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void
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recordProducer(const DynInstPtr &inst)
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{
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addToProducers(inst);
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}
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/** Process FU completion event. */
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void processFUCompletion(const DynInstPtr &inst, int fu_idx);
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/**
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* Schedules ready instructions, adding the ready ones (oldest first) to
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* the queue to execute.
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*/
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void scheduleReadyInsts();
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/** Schedules a single specific non-speculative instruction. */
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void scheduleNonSpec(const InstSeqNum &inst);
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/**
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* Commits all instructions up to and including the given sequence number,
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* for a specific thread.
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*/
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void commit(const InstSeqNum &inst, ThreadID tid = 0);
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/** Wakes all dependents of a completed instruction. */
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int wakeDependents(const DynInstPtr &completed_inst);
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/** Adds a ready memory instruction to the ready list. */
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void addReadyMemInst(const DynInstPtr &ready_inst);
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/**
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* Reschedules a memory instruction. It will be ready to issue once
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* replayMemInst() is called.
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*/
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void rescheduleMemInst(const DynInstPtr &resched_inst);
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/** Replays a memory instruction. It must be rescheduled first. */
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void replayMemInst(const DynInstPtr &replay_inst);
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/**
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* Defers a memory instruction when its DTB translation incurs a hw
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* page table walk.
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*/
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void deferMemInst(const DynInstPtr &deferred_inst);
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/** Defers a memory instruction when it is cache blocked. */
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void blockMemInst(const DynInstPtr &blocked_inst);
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/** Notify instruction queue that a previous blockage has resolved */
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void cacheUnblocked();
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/** Indicates an ordering violation between a store and a load. */
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void violation(const DynInstPtr &store, const DynInstPtr &faulting_load);
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/**
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* Squashes instructions for a thread. Squashing information is obtained
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* from the time buffer.
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*/
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void squash(ThreadID tid);
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/** Returns the number of used entries for a thread. */
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unsigned getCount(ThreadID tid) { return count[tid]; };
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/** Debug function to print all instructions. */
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void printInsts();
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private:
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/** Does the actual squashing. */
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void doSquash(ThreadID tid);
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/////////////////////////
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// Various pointers
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/////////////////////////
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/** Pointer to the CPU. */
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CPU *cpu;
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/** Cache interface. */
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memory::MemInterface *dcacheInterface;
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/** Pointer to IEW stage. */
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IEW *iewStage;
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/** The memory dependence unit, which tracks/predicts memory dependences
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* between instructions.
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*/
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MemDepUnit memDepUnit[MaxThreads];
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/** The queue to the execute stage. Issued instructions will be written
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* into it.
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*/
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TimeBuffer<IssueStruct> *issueToExecuteQueue;
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/** The backwards time buffer. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to read information from timebuffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Function unit pool. */
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FUPool *fuPool;
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//////////////////////////////////////
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// Instruction lists, ready queues, and ordering
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//////////////////////////////////////
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/** List of all the instructions in the IQ (some of which may be issued). */
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std::list<DynInstPtr> instList[MaxThreads];
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/** List of instructions that are ready to be executed. */
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std::list<DynInstPtr> instsToExecute;
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/** List of instructions waiting for their DTB translation to
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* complete (hw page table walk in progress).
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*/
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std::list<DynInstPtr> deferredMemInsts;
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/** List of instructions that have been cache blocked. */
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std::list<DynInstPtr> blockedMemInsts;
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/** List of instructions that were cache blocked, but a retry has been seen
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* since, so they can now be retried. May fail again go on the blocked list.
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*/
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std::list<DynInstPtr> retryMemInsts;
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/**
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* Struct for comparing entries to be added to the priority queue.
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* This gives reverse ordering to the instructions in terms of
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* sequence numbers: the instructions with smaller sequence
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* numbers (and hence are older) will be at the top of the
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* priority queue.
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*/
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struct PqCompare
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{
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bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const;
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};
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typedef std::priority_queue<
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DynInstPtr, std::vector<DynInstPtr>, PqCompare> ReadyInstQueue;
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/** List of ready instructions, per op class. They are separated by op
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* class to allow for easy mapping to FUs.
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*/
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ReadyInstQueue readyInsts[Num_OpClasses];
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/** List of non-speculative instructions that will be scheduled
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* once the IQ gets a signal from commit. While it's redundant to
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* have the key be a part of the value (the sequence number is stored
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* inside of DynInst), when these instructions are woken up only
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* the sequence number will be available. Thus it is most efficient to be
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* able to search by the sequence number alone.
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*/
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std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
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typedef std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
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/** Entry for the list age ordering by op class. */
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struct ListOrderEntry
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{
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OpClass queueType;
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InstSeqNum oldestInst;
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};
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/** List that contains the age order of the oldest instruction of each
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* ready queue. Used to select the oldest instruction available
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* among op classes.
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* @todo: Might be better to just move these entries around instead
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* of creating new ones every time the position changes due to an
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* instruction issuing. Not sure std::list supports this.
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*/
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std::list<ListOrderEntry> listOrder;
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typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
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/** Tracks if each ready queue is on the age order list. */
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bool queueOnList[Num_OpClasses];
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/** Iterators of each ready queue. Points to their spot in the age order
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* list.
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*/
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ListOrderIt readyIt[Num_OpClasses];
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/** Add an op class to the age order list. */
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void addToOrderList(OpClass op_class);
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/**
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* Called when the oldest instruction has been removed from a ready queue;
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* this places that ready queue into the proper spot in the age order list.
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*/
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void moveToYoungerInst(ListOrderIt age_order_it);
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DependencyGraph<DynInstPtr> dependGraph;
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//////////////////////////////////////
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// Various parameters
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//////////////////////////////////////
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/** IQ sharing policy for SMT. */
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SMTQueuePolicy iqPolicy;
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/** Number of Total Threads*/
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ThreadID numThreads;
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/** Pointer to list of active threads. */
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std::list<ThreadID> *activeThreads;
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/** Per Thread IQ count */
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unsigned count[MaxThreads];
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/** Max IQ Entries Per Thread */
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unsigned maxEntries[MaxThreads];
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/** Number of free IQ entries left. */
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unsigned freeEntries;
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/** The number of entries in the instruction queue. */
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unsigned numEntries;
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/** The total number of instructions that can be issued in one cycle. */
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unsigned totalWidth;
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/** The number of physical registers in the CPU. */
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unsigned numPhysRegs;
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/** Number of instructions currently in flight to FUs */
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int wbOutstanding;
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/** Delay between commit stage and the IQ.
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* @todo: Make there be a distinction between the delays within IEW.
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*/
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Cycles commitToIEWDelay;
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/** The sequence number of the squashed instruction. */
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InstSeqNum squashedSeqNum[MaxThreads];
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/** A cache of the recently woken registers. It is 1 if the register
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* has been woken up recently, and 0 if the register has been added
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* to the dependency graph and has not yet received its value. It
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* is basically a secondary scoreboard, and should pretty much mirror
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* the scoreboard that exists in the rename map.
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*/
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std::vector<bool> regScoreboard;
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/** Adds an instruction to the dependency graph, as a consumer. */
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bool addToDependents(const DynInstPtr &new_inst);
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/** Adds an instruction to the dependency graph, as a producer. */
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void addToProducers(const DynInstPtr &new_inst);
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/** Moves an instruction to the ready queue if it is ready. */
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void addIfReady(const DynInstPtr &inst);
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/** Debugging function to count how many entries are in the IQ. It does
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* a linear walk through the instructions, so do not call this function
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* during normal execution.
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*/
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int countInsts();
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/** Debugging function to dump all the list sizes, as well as print
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* out the list of nonspeculative instructions. Should not be used
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* in any other capacity, but it has no harmful sideaffects.
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*/
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void dumpLists();
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/** Debugging function to dump out all instructions that are in the
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* IQ.
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*/
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void dumpInsts();
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struct IQStats : public statistics::Group
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{
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IQStats(CPU *cpu, const unsigned &total_width);
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/** Stat for number of instructions added. */
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statistics::Scalar instsAdded;
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/** Stat for number of non-speculative instructions added. */
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statistics::Scalar nonSpecInstsAdded;
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statistics::Scalar instsIssued;
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/** Stat for number of integer instructions issued. */
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statistics::Scalar intInstsIssued;
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/** Stat for number of floating point instructions issued. */
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statistics::Scalar floatInstsIssued;
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/** Stat for number of branch instructions issued. */
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statistics::Scalar branchInstsIssued;
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/** Stat for number of memory instructions issued. */
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statistics::Scalar memInstsIssued;
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/** Stat for number of miscellaneous instructions issued. */
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statistics::Scalar miscInstsIssued;
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/** Stat for number of squashed instructions that were ready to
|
|
* issue. */
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statistics::Scalar squashedInstsIssued;
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/** Stat for number of squashed instructions examined when
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* squashing. */
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|
statistics::Scalar squashedInstsExamined;
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/** Stat for number of squashed instruction operands examined when
|
|
* squashing.
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|
*/
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|
statistics::Scalar squashedOperandsExamined;
|
|
/** Stat for number of non-speculative instructions removed due to
|
|
* a squash.
|
|
*/
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|
statistics::Scalar squashedNonSpecRemoved;
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|
// Also include number of instructions rescheduled and replayed.
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|
|
|
/** Distribution of number of instructions in the queue.
|
|
* @todo: Need to create struct to track the entry time for each
|
|
* instruction. */
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|
// statistics::VectorDistribution queueResDist;
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|
/** Distribution of the number of instructions issued. */
|
|
statistics::Distribution numIssuedDist;
|
|
/** Distribution of the cycles it takes to issue an instruction.
|
|
* @todo: Need to create struct to track the ready time for each
|
|
* instruction. */
|
|
// statistics::VectorDistribution issueDelayDist;
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|
|
|
/** Number of times an instruction could not be issued because a
|
|
* FU was busy.
|
|
*/
|
|
statistics::Vector statFuBusy;
|
|
// statistics::Vector dist_unissued;
|
|
/** Stat for total number issued for each instruction type. */
|
|
statistics::Vector2d statIssuedInstType;
|
|
|
|
/** Number of instructions issued per cycle. */
|
|
statistics::Formula issueRate;
|
|
|
|
/** Number of times the FU was busy. */
|
|
statistics::Vector fuBusy;
|
|
/** Number of times the FU was busy per instruction issued. */
|
|
statistics::Formula fuBusyRate;
|
|
} iqStats;
|
|
|
|
public:
|
|
struct IQIOStats : public statistics::Group
|
|
{
|
|
IQIOStats(statistics::Group *parent);
|
|
statistics::Scalar intInstQueueReads;
|
|
statistics::Scalar intInstQueueWrites;
|
|
statistics::Scalar intInstQueueWakeupAccesses;
|
|
statistics::Scalar fpInstQueueReads;
|
|
statistics::Scalar fpInstQueueWrites;
|
|
statistics::Scalar fpInstQueueWakeupAccesses;
|
|
statistics::Scalar vecInstQueueReads;
|
|
statistics::Scalar vecInstQueueWrites;
|
|
statistics::Scalar vecInstQueueWakeupAccesses;
|
|
|
|
statistics::Scalar intAluAccesses;
|
|
statistics::Scalar fpAluAccesses;
|
|
statistics::Scalar vecAluAccesses;
|
|
} iqIOStats;
|
|
};
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|
|
|
} // namespace o3
|
|
} // namespace gem5
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#endif //__CPU_O3_INST_QUEUE_HH__
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