gem5/src/cpu/o3 at 6ef9691035623ba6945e237a41f0dca04db637bb - gem5

base_dyn_inst.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

bpred_unit_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

bpred_unit.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

bpred_unit.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

checker_builder.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

comm.hh

O3: When squashing, restore the macroop that should be used for fetching.

2011-08-14 17:41:34 -07:00

commit_impl.hh

event: minor cleanup

2011-09-22 18:59:55 -07:00

commit.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

commit.hh

includes: fix up code after sorting

2011-04-15 10:44:14 -07:00

cpu_builder.cc

o3-smt: enforce numThreads parameter for SMT SE mode

2009-07-25 00:50:27 -04:00

cpu_policy.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

cpu.cc

O3: Add stat that counts how many cycles the O3 cpu was quiesced.

2011-12-01 00:15:22 -08:00

cpu.hh

O3: Add stat that counts how many cycles the O3 cpu was quiesced.

2011-12-01 00:15:22 -08:00

decode_impl.hh

O3: When squashing, restore the macroop that should be used for fetching.

2011-08-14 17:41:34 -07:00

decode.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

decode.hh

Move sched_list.hh and timebuf.hh from src/base to src/cpu.

2011-01-03 14:35:47 -08:00

dep_graph.hh

ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.

2010-10-31 00:07:20 -07:00

dyn_inst_impl.hh

Syscall: Make the syscall function available in both SE and FS modes.

2011-09-19 02:46:48 -07:00

dyn_inst.cc

O3: Generaize the O3 IMPL class so it isn't split out by ISA.

2008-10-09 00:10:02 -07:00

dyn_inst.hh

Syscall: Make the syscall function available in both SE and FS modes.

2011-09-19 02:46:48 -07:00

fetch_impl.hh

gcc: fix unused variable warnings from GCC 4.6.1

2011-12-13 11:49:27 -08:00

fetch.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

fetch.hh

Decode: Pull instruction decoding out of the StaticInst class into its own.

2011-09-09 02:30:01 -07:00

free_list.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

free_list.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

fu_pool.cc

params: Deprecate old-style constructors; update most SimObject constructors.

2007-08-30 15:16:59 -04:00

fu_pool.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

FuncUnitConfig.py

CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

2010-11-15 14:04:04 -06:00

FUPool.py

CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

2010-11-15 14:04:04 -06:00

iew_impl.hh

O3: Squash the violator and younger instructions instead not all insts.

2011-08-19 15:08:05 -05:00

iew.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

iew.hh

O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.

2011-05-23 10:40:19 -05:00

impl.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

inst_queue_impl.hh

event: minor cleanup

2011-09-22 18:59:55 -07:00

inst_queue.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

inst_queue.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

isa_specific.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

lsq_impl.hh

LSQ: Only trigger a memory violation with a load/load if the value changes.

2011-09-13 12:58:08 -04:00

lsq_unit_impl.hh

O3: Tidy up some DPRINTFs in the LSQ.

2011-09-27 00:25:26 -07:00

lsq_unit.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

lsq_unit.hh

Faults: Replace calls to genMachineCheckFault with M5PanicFault.

2011-09-27 00:24:43 -07:00

lsq.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

lsq.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

mem_dep_unit_impl.hh

LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

2011-08-19 15:08:07 -05:00

mem_dep_unit.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

mem_dep_unit.hh

LSQ: Add some better dprintfs for storeset predictor.

2011-08-19 15:08:05 -05:00

O3Checker.py

python: Move more code into m5.util allow SCons to use that code.

2009-09-22 15:24:16 -07:00

O3CPU.py

O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

2011-12-01 00:15:22 -08:00

regfile.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

rename_impl.hh

GCC: Get everything working with gcc 4.6.1.

2011-10-31 01:09:44 -07:00

rename_map.cc

o3: missing newlines on some dprintfs

2011-06-10 22:15:32 -04:00

rename_map.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

rename.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

rename.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

rob_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

rob.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

rob.hh

includes: fix up code after sorting

2011-04-15 10:44:14 -07:00

sat_counter.cc

Merge ktlim@zizzer:/bk/newmem

2006-06-02 18:19:50 -04:00

sat_counter.hh

types: Move stuff for global types into src/base/types.hh

2009-05-17 14:34:50 -07:00

SConscript

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

SConsopts

cpu_models: get rid of cpu_models.py and move the stuff into SCons

2010-02-26 18:14:48 -08:00

scoreboard.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

scoreboard.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

store_set.cc

LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

2011-08-19 15:08:07 -05:00

store_set.hh

LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

2011-08-19 15:08:07 -05:00

thread_context_impl.hh

Fix bugs due to interaction between SEV instructions and O3 pipeline

2011-08-19 15:08:07 -05:00

thread_context.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

thread_context.hh

Decode: Pull instruction decoding out of the StaticInst class into its own.

2011-09-09 02:30:01 -07:00

thread_state.hh

Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.

2009-07-08 23:02:22 -07:00