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GCC: Get everything working with gcc 4.6.1.

Browse Source 
And by "everything" I mean all the quick regressions.
This commit is contained in:
Gabe Black
2011-10-31 01:09:44 -07:00
parent ce2f9625f4
commit d735abe5da
29 changed files with 60 additions and 114 deletions
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2
src/SConscript
View File

@@ -851,6 +851,8 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
swig_env.Append(CCFLAGS='-Wno-uninitialized')
swig_env.Append(CCFLAGS='-Wno-sign-compare')
swig_env.Append(CCFLAGS='-Wno-parentheses')
swig_env.Append(CCFLAGS='-Wno-unused-label')
swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
werror_env = new_env.Clone()
werror_env.Append(CCFLAGS='-Werror')

7
src/arch/alpha/ev5.cc
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@@ -209,8 +209,6 @@ int break_ipl = -1;
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
uint64_t old;
if (tc->misspeculating())
return;
@@ -262,12 +260,11 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
case IPR_PALtemp23:
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->context(old, val, tc);
tc->getKernelStats()->context(ipr[idx], val, tc);
#endif
ipr[idx] = val;
break;
case IPR_DTB_PTE:

2
src/arch/alpha/isa/mem.isa
View File

@@ -388,7 +388,7 @@ def template MiscExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Addr EA M5_VAR_USED;
Fault fault = NoFault;
%(fp_enable_check)s;

18
src/arch/arm/isa/formats/fp.isa
View File

@@ -561,20 +561,22 @@ let {{
}
}
case 0xa:
if (q)
return new Unknown(machInst);
if (b) {
return decodeNeonUSThreeReg<VpminD, VpminQ>(
q, u, size, machInst, vd, vn, vm);
return decodeNeonUSThreeUSReg<VpminD>(
u, size, machInst, vd, vn, vm);
} else {
return decodeNeonUSThreeReg<VpmaxD, VpmaxQ>(
q, u, size, machInst, vd, vn, vm);
return decodeNeonUSThreeUSReg<VpmaxD>(
u, size, machInst, vd, vn, vm);
}
case 0xb:
if (b) {
if (u) {
if (u || q) {
return new Unknown(machInst);
} else {
return decodeNeonUThreeReg<NVpaddD, NVpaddQ>(
q, size, machInst, vd, vn, vm);
return decodeNeonUThreeUSReg<NVpaddD>(
size, machInst, vd, vn, vm);
}
} else {
if (u) {
@@ -1542,7 +1544,7 @@ let {{
else
return new NVswpD<uint64_t>(machInst, vd, vm);
case 0x1:
return decodeNeonUTwoMiscReg<NVtrnD, NVtrnQ>(
return decodeNeonUTwoMiscSReg<NVtrnD, NVtrnQ>(
q, size, machInst, vd, vm);
case 0x2:
return decodeNeonUTwoMiscReg<NVuzpD, NVuzpQ>(

4
src/arch/arm/isa/insts/fp.isa
View File

@@ -447,7 +447,7 @@ let {{
exec_output = ""
singleSimpleCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc;
FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
FpDest = %(op)s;
'''
singleCode = singleSimpleCode + '''
@@ -457,7 +457,7 @@ let {{
"%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
doubleCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc;
FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
double dest = %(op)s;
FpDestP0_uw = dblLow(dest);
FpDestP1_uw = dblHi(dest);

19
src/arch/arm/isa/insts/m5ops.isa
View File

@@ -54,9 +54,7 @@ let {{
armCode = '''
#if FULL_SYSTEM
PseudoInst::arm(xc->tcBase());
#endif
'''
armIop = InstObjParams("arm", "Arm", "PredOp",
{ "code": armCode,
@@ -67,9 +65,7 @@ let {{
exec_output += PredOpExecute.subst(armIop)
quiesceCode = '''
#if FULL_SYSTEM
PseudoInst::quiesce(xc->tcBase());
#endif
'''
quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
{ "code": quiesceCode,
@@ -80,9 +76,7 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceIop)
quiesceNsCode = '''
#if FULL_SYSTEM
PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
#endif
'''
quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
@@ -94,9 +88,7 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
quiesceCyclesCode = '''
#if FULL_SYSTEM
PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
#endif
'''
quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
@@ -108,11 +100,9 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
quiesceTimeCode = '''
#if FULL_SYSTEM
uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
R0 = bits(qt_val, 31, 0);
R1 = bits(qt_val, 63, 32);
#endif
'''
quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
@@ -188,9 +178,7 @@ let {{
exec_output += PredOpExecute.subst(m5exitIop)
loadsymbolCode = '''
#if FULL_SYSTEM
PseudoInst::loadsymbol(xc->tcBase());
#endif
'''
loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
@@ -204,6 +192,9 @@ let {{
initparamCode = '''
#if FULL_SYSTEM
Rt = PseudoInst::initParam(xc->tcBase());
#else
PseudoInst::panicFsOnlyPseudoInst("initparam");
Rt = 0;
#endif
'''
@@ -260,11 +251,9 @@ let {{
exec_output += PredOpExecute.subst(m5checkpointIop)
m5readfileCode = '''
#if FULL_SYSTEM
int n = 4;
uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
#endif
'''
m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
{ "code": m5readfileCode,
@@ -291,9 +280,7 @@ let {{
exec_output += PredOpExecute.subst(m5switchcpuIop)
m5addsymbolCode = '''
#if FULL_SYSTEM
PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
#endif
'''
m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
{ "code": m5addsymbolCode,

7
src/arch/arm/isa/insts/macromem.isa
View File

@@ -563,15 +563,16 @@ let {{
let {{
exec_output = ''
for type in ('uint8_t', 'uint16_t', 'uint32_t'):
for typeSize in (8, 16, 32):
for sRegs in 1, 2:
for dRegs in range(sRegs, 5):
for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)):
for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop",
"MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop",
"MicroPackNeon%(dRegs)dto%(sRegs)dUop"):
Name = format % { "sRegs" : sRegs * 2,
"dRegs" : dRegs * 2 }
substDict = { "class_name" : Name, "targs" : type }
substDict = { "class_name" : Name,
"targs" : "uint%d_t" % typeSize }
exec_output += MicroNeonExecDeclare.subst(substDict)
}};

16
src/arch/arm/isa/insts/neon.isa
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@@ -1619,10 +1619,8 @@ let {{
threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode)
threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode)
threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes,
threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes,
2, vaddCode, pairwise=True)
threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes,
4, vaddCode, pairwise=True)
vaddlwCode = '''
destElem = (BigElement)srcElem1 + (BigElement)srcElem2;
'''
@@ -2113,11 +2111,9 @@ let {{
'''
threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode)
threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True)
threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True)
threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True)
threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True)
threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True)
threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True)
vqdmulhCode = '''
FPSCR fpscr = (FPSCR) FpscrQc;
@@ -3140,8 +3136,10 @@ let {{
destReg.elements[i + 1] = mid;
}
'''
twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode)
twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode)
twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp",
smallUnsignedTypes, 2, vtrnCode)
twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp",
smallUnsignedTypes, 4, vtrnCode)
vuzpCode = '''
Element mid[eCount];

4
src/arch/arm/isa/templates/mem.isa
View File

@@ -1112,7 +1112,7 @@ def template LoadRegConstructor {{
(IntRegIndex)_index)
{
%(constructor)s;
bool conditional = false;
bool conditional M5_VAR_USED = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
@@ -1166,7 +1166,7 @@ def template LoadImmConstructor {{
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
{
%(constructor)s;
bool conditional = false;
bool conditional M5_VAR_USED = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {

8
src/arch/mips/isa/decoder.isa
View File

@@ -497,8 +497,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: mttc1({{
uint64_t data = xc->readRegOtherThread(RD +
FP_Base_DepTag);
data = insertBits(data, top_bit,
bottom_bit, Rt);
data = insertBits(data, MT_H ? 63 : 31,
MT_H ? 32 : 0, Rt);
xc->setRegOtherThread(RD + FP_Base_DepTag,
data);
}});
@@ -532,7 +532,7 @@ decode OPCODE_HI default Unknown::unknown() {
panic("FP Control Value (%d) "
"Not Available. Ignoring "
"Access to Floating Control "
"Status Register", FS);
"S""tatus Register", FS);
}
xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
}});
@@ -776,7 +776,6 @@ decode OPCODE_HI default Unknown::unknown() {
bits(pageGrain, pageGrain.esp) == 1) {
SP = 1;
}
IndexReg index = Index;
Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
}});
0x06: tlbwr({{
@@ -842,7 +841,6 @@ decode OPCODE_HI default Unknown::unknown() {
bits(pageGrain, pageGrain.esp) == 1) {
SP = 1;
}
IndexReg index = Index;
Ptr->insertAt(newEntry, Random, SP);
}});

22
src/arch/mips/isa/formats/mt.isa
View File

@@ -107,7 +107,7 @@ def template ThreadRegisterExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
int64_t data;
int64_t data M5_VAR_USED;
%(op_decl)s;
%(op_rd)s;
@@ -126,17 +126,6 @@ def template ThreadRegisterExecute {{
} else if (vpeControl.targTC > mvpConf0.ptc) {
data = -1;
} else {
int top_bit = 0;
int bottom_bit = 0;
if (MT_H == 1) {
top_bit = 63;
bottom_bit = 32;
} else {
top_bit = 31;
bottom_bit = 0;
}
%(code)s;
}
} else {
@@ -203,10 +192,11 @@ def format MT_MFTR(code, *flags) {{
flags += ('IsNonSpeculative', )
# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
code += 'if (MT_H == 1) {\n'
code += 'data = bits(data, top_bit, bottom_bit);\n'
code += '}\n'
code += 'Rd = data;\n'
code += '''
if (MT_H)
data = bits(data, 63, 32);
Rd = data;
'''
iop = InstObjParams(name, Name, 'MTOp', code, flags)
header_output = BasicDeclare.subst(iop)

2
src/arch/mips/isa/includes.isa
View File

@@ -52,7 +52,9 @@ output decoder {{
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pagetable.hh"
#include "arch/mips/pra_constants.hh"
#include "arch/mips/tlb.hh"
#include "arch/mips/utility.hh"
#include "base/loader/symtab.hh"
#include "base/cprintf.hh"

2
src/arch/mips/tlb.cc
View File

@@ -129,7 +129,6 @@ int
TLB::probeEntry(Addr vpn, uint8_t asn) const
{
// assume not found...
PTE *retval = NULL;
int Ind = -1;
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
@@ -144,7 +143,6 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const
if (((vpn & InvMask) == (VPN & InvMask)) &&
(pte->G || (asn == pte->asid))) {
// We have a VPN + ASID Match
retval = pte;
Ind = index;
break;
}

2
src/arch/power/isa/formats/mem.isa
View File

@@ -123,7 +123,7 @@ def template LoadCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Addr M5_VAR_USED EA;
Fault fault = NoFault;
%(op_decl)s;

2
src/arch/power/tlb.cc
View File

@@ -118,7 +118,6 @@ int
TLB::probeEntry(Addr vpn,uint8_t asn) const
{
// assume not found...
PowerISA::PTE *retval = NULL;
int Ind = -1;
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
@@ -132,7 +131,6 @@ TLB::probeEntry(Addr vpn,uint8_t asn) const
&& (pte->G || (asn == pte->asid))) {
// We have a VPN + ASID Match
retval = pte;
Ind = index;
break;
}

5
src/arch/sparc/isa/formats/mem/util.isa
View File

@@ -326,9 +326,8 @@ let {{
'''
TruncateEA = '''
#if !FULL_SYSTEM
EA = Pstate<3:> ? EA<31:0> : EA;
#endif
if (!FULL_SYSTEM)
EA = Pstate<3:> ? EA<31:0> : EA;
'''
}};

3
src/arch/x86/isa/microops/base.isa
View File

@@ -59,7 +59,8 @@ let {{
''' + generatorNameTemplate + '''(StaticInstPtr curMacroop)
{
static const char *macrocodeBlock = romMnemonic;
static const ExtMachInst dummyExtMachInst;
static const ExtMachInst dummyExtMachInst = \
X86ISA::NoopMachInst;
static const EmulEnv dummyEmulEnv(0, 0, 1, 1, 1);
Macroop * macroop = dynamic_cast<Macroop *>(curMacroop.get());

1
src/base/inet.cc
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@@ -30,6 +30,7 @@
* Gabe Black
*/
#include <cstddef>
#include <cstdio>
#include <sstream>
#include <string>

3
src/cpu/base.cc
View File

@@ -240,8 +240,7 @@ BaseCPU::startup()
if (params()->progress_interval) {
Tick num_ticks = ticks(params()->progress_interval);
Event *event;
event = new CPUProgressEvent(this, num_ticks);
new CPUProgressEvent(this, num_ticks);
}
}

8
src/cpu/inorder/cpu.cc
View File

@@ -211,7 +211,6 @@ InOrderCPU::InOrderCPU(Params *params)
lastRunningCycle(0),
instsPerSwitch(0)
{
ThreadID active_threads;
cpu_params = params;
resPool = new ResourcePool(this, params);
@@ -219,10 +218,8 @@ InOrderCPU::InOrderCPU(Params *params)
// Resize for Multithreading CPUs
thread.resize(numThreads);
#if FULL_SYSTEM
active_threads = 1;
#else
active_threads = params->workload.size();
#if !FULL_SYSTEM
ThreadID active_threads = params->workload.size();
if (active_threads > MaxThreads) {
panic("Workload Size too large. Increase the 'MaxThreads'"
@@ -1124,7 +1121,6 @@ InOrderCPU::updateThreadPriority()
//DEFAULT TO ROUND ROBIN SCHEME
//e.g. Move highest priority to end of thread list
list<ThreadID>::iterator list_begin = activeThreads.begin();
list<ThreadID>::iterator list_end = activeThreads.end();
unsigned high_thread = *list_begin;

2
src/cpu/legiontrace.cc
View File

@@ -167,7 +167,7 @@ Trace::LegionTraceRecord::dump()
bool diffTnpc = false;
bool diffTstate = false;
bool diffTt = false;
bool diffTba = false;
bool diffTba M5_VAR_USED = false;
bool diffHpstate = false;
bool diffHtstate = false;
bool diffHtba = false;

1
src/cpu/o3/cpu.cc
View File

@@ -1653,7 +1653,6 @@ FullO3CPU<Impl>::updateThreadPriority()
//DEFAULT TO ROUND ROBIN SCHEME
//e.g. Move highest priority to end of thread list
list<ThreadID>::iterator list_begin = activeThreads.begin();
list<ThreadID>::iterator list_end = activeThreads.end();
unsigned high_thread = *list_begin;

16
src/cpu/o3/rename_impl.hh
View File

@@ -1215,24 +1215,16 @@ template <class Impl>
void
DefaultRename<Impl>::readFreeEntries(ThreadID tid)
{
bool updated = false;
if (fromIEW->iewInfo[tid].usedIQ) {
freeEntries[tid].iqEntries =
fromIEW->iewInfo[tid].freeIQEntries;
updated = true;
}
if (fromIEW->iewInfo[tid].usedIQ)
freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
if (fromIEW->iewInfo[tid].usedLSQ) {
freeEntries[tid].lsqEntries =
fromIEW->iewInfo[tid].freeLSQEntries;
updated = true;
}
if (fromIEW->iewInfo[tid].usedLSQ)
freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
if (fromCommit->commitInfo[tid].usedROB) {
freeEntries[tid].robEntries =
fromCommit->commitInfo[tid].freeROBEntries;
emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
updated = true;
}
DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",

2
src/mem/cache/tags/iic.cc vendored
View File

@@ -393,10 +393,8 @@ IIC::freeReplacementBlock(PacketList & writebacks)
unsigned long
IIC::getFreeDataBlock(PacketList & writebacks)
{
struct IICTag *tag_ptr;
unsigned long data_ptr;
tag_ptr = NULL;
/* find data block */
while (blkFreelist.empty()) {
freeReplacementBlock(writebacks);

7
src/mem/ruby/network/orion/Clock.cc
View File

@@ -137,13 +137,10 @@ void Clock::init()
double router_diagonal = m_orion_cfg_ptr->get<double>("ROUTER_DIAGONAL");
double Clockwire = m_tech_param_ptr->get_ClockCap();
double Reswire = m_tech_param_ptr->get_Reswire();
double htree_clockcap;
double htree_res;
int k;
double h;
double cap_clock_buf = 0;
double BufferNMOSOffCurrent = m_tech_param_ptr->get_BufferNMOSOffCurrent();
double BufferPMOSOffCurrent = m_tech_param_ptr->get_BufferPMOSOffCurrent();
@@ -151,7 +148,6 @@ void Clock::init()
if (m_tech_param_ptr->is_trans_type_hvt() || m_tech_param_ptr->is_trans_type_nvt())
{
htree_clockcap = (4+4+2+2)*(router_diagonal*1e-6)*Clockwire;
htree_res = (4+4+2+2)*(router_diagonal*1e-6)*Reswire;
wire.calc_opt_buffering(&k, &h, ((4+4+2+2)*router_diagonal*1e-6));
i_static_nmos = BufferNMOSOffCurrent*h*k*15;
@@ -160,15 +156,12 @@ void Clock::init()
else
{
htree_clockcap = (8+4+4+4+4)*(router_diagonal*1e-6)*Clockwire;
htree_res = (8+4+4+4+4)*(router_diagonal*1e-6)*Reswire;
wire.calc_opt_buffering(&k, &h, ((4+4+2+2)*router_diagonal*1e-6));
i_static_nmos = BufferNMOSOffCurrent*h*k*29;
i_static_pmos = BufferPMOSOffCurrent*h*k*15;
}
cap_clock_buf = ((double)k)*cap_clock*h;
m_e_htree = (htree_clockcap+cap_clock)*e_factor;
}
else

1
src/mem/ruby/system/PersistentTable.hh
View File

@@ -41,6 +41,7 @@
class PersistentTableEntry
{
public:
PersistentTableEntry() {}
void print(std::ostream& out) const {}
NetDest m_starving;

3
src/mem/ruby/system/PseudoLRUPolicy.hh
View File

@@ -64,8 +64,6 @@ inline
PseudoLRUPolicy::PseudoLRUPolicy(Index num_sets, Index assoc)
: AbstractReplacementPolicy(num_sets, assoc)
{
int num_tree_nodes;
// associativity cannot exceed capacity of tree representation
assert(num_sets > 0 && assoc > 1 && assoc <= (Index) sizeof(uint64)*4);
@@ -84,7 +82,6 @@ PseudoLRUPolicy::PseudoLRUPolicy(Index num_sets, Index assoc)
m_num_levels++;
}
assert(m_num_levels < sizeof(unsigned int)*4);
num_tree_nodes = (1 << m_num_levels) - 1;
m_trees = new uint64[m_num_sets];
for (unsigned i = 0; i < m_num_sets; i++) {
m_trees[i] = 0;

1
src/python/m5/params.py
View File

@@ -164,6 +164,7 @@ class ParamDesc(object):
return self.ptype(value)
def cxx_predecls(self, code):
code('#include <cstddef>')
self.ptype.cxx_predecls(code)
def swig_predecls(self, code):

4
src/python/swig/pyobject.cc
View File

@@ -94,10 +94,6 @@ int
connectPorts(SimObject *o1, const std::string &name1, int i1,
SimObject *o2, const std::string &name2, int i2)
{
MemObject *mo1, *mo2;
mo1 = dynamic_cast<MemObject*>(o1);
mo2 = dynamic_cast<MemObject*>(o2);
#if FULL_SYSTEM
EtherObject *eo1, *eo2;
EtherDevice *ed1, *ed2;