Steve Reinhardt 6dc599ea9b mem: fix functional accesses to deal with coherence change ...

We can't just obliviously return the first valid cache block
we find any more... see comments for details.

2010-09-09 14:40:19 -04:00

..

cache

mem: fix functional accesses to deal with coherence change

2010-09-09 14:40:19 -04:00

config

Fixes to get prefetching working again.

2009-02-16 08:56:40 -08:00

protocol

MOESI_hammer: fixed bug for dma reads in single cpu systems

2010-08-24 12:06:53 -07:00

ruby

testers: move testers to a new directory

2010-08-24 12:07:22 -07:00

slicc

ruby: Stall and wait input messages instead of recycling

2010-08-20 11:46:14 -07:00

bridge.cc

mem: fix functional accesses to deal with coherence change

2010-09-09 14:40:19 -04:00

bridge.hh

includes: use base/types.hh not inttypes.h or stdint.h

2009-05-17 14:34:51 -07:00

Bridge.py

DMA: Add IOCache and fix bus bridge to optionally only send requests one

2007-08-10 16:14:01 -04:00

bus.cc

bus: clean up default responder code.

2010-08-17 05:06:21 -07:00

bus.hh

bus: clean up default responder code.

2010-08-17 05:06:21 -07:00

Bus.py

bus: clean up default responder code.

2010-08-17 05:06:21 -07:00

dram.cc

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

2008-09-10 14:26:15 -04:00

dram.hh

stats: Fix all stats usages to deal with template fixes

2009-03-05 19:09:53 -08:00

mem_object.cc

params: Get rid of the remnants of the old style parameter configuration stuff.

2008-08-11 12:22:17 -07:00

mem_object.hh

params: Get rid of the remnants of the old style parameter configuration stuff.

2008-08-11 12:22:17 -07:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mport.cc

X86: Add a function which gets called when an interrupt message has been delivered.

2009-04-19 03:54:11 -07:00

mport.hh

Create a message port for sending messages as apposed to reading/writing a memory range.

2008-10-12 12:08:51 -07:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet.cc

mem: fix functional accesses to deal with coherence change

2010-09-09 14:40:19 -04:00

packet.hh

mem: fix dumb typo in copyrights

2010-08-25 14:08:27 -07:00

page_table.cc

util: do checkpoint aggregation more cleanly, fix last changeset.

2010-01-19 22:03:44 -08:00

page_table.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

physical.cc

util: do checkpoint aggregation more cleanly, fix last changeset.

2010-01-19 22:03:44 -08:00

physical.hh

types: clean up types, especially signed vs unsigned

2009-06-04 23:21:12 -07:00

PhysicalMemory.py

Make default PhysicalMemory latency slightly more realistic.

2008-08-03 18:13:29 -04:00

port_impl.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

port.cc

types: clean up types, especially signed vs unsigned

2009-06-04 23:21:12 -07:00

port.hh

types: clean up types, especially signed vs unsigned

2009-06-04 23:21:12 -07:00

request.hh

MEM: Make CLREX a first class request operation and clear locks in caches when it in received

2010-08-23 11:18:41 -05:00

SConscript

ruby: Convert most Ruby objects to M5 SimObjects.

2010-01-29 20:29:17 -08:00

tport.cc

Port: Only indicate that a SimpleTimingPort is drained if its send event is

2010-07-22 18:54:37 +01:00

tport.hh

Clean up the SimpleTimingPort class a little bit.

2008-11-10 11:51:18 -08:00

translating_port.cc

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

translating_port.hh

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

vport.cc

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

vport.hh

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00