Nils Asmussen 6d3bf34a2a arch-riscv: show names of MiscRegs on accesses. ...

Printing the number of the MiscRegs makes it hard to debug problems.
Therefore, this commit adds a name table and prints the name of the
register.

Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25649
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

2020-04-29 11:41:55 +00:00

..

arch

arch-riscv: show names of MiscRegs on accesses.

2020-04-29 11:41:55 +00:00

base

base,misc: Added version to code

2020-04-22 19:50:39 +00:00

cpu

cpu,configs: let RISC-V use the PT walker cache.

2020-04-29 11:41:55 +00:00

dev

dev,cpu: Make two very generic enums ScopedEnums.

2020-04-20 22:49:11 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

misc: Delete authors lists from documentation related files.

2020-02-17 21:50:09 +00:00

gpu-compute

base,arch-hsail: Fix GPU build

2020-04-03 21:51:57 +00:00

kern

base,arch,sim,cpu: Move object file loader components into a namespace.

2020-04-22 06:08:54 +00:00

learning_gem5

mem-ruby: Replace SLICC queueMemory calls with enqueue

2020-04-08 23:40:57 +00:00

mem

mem-ruby: Fix Ruby handling of functional requests

2020-04-23 00:23:30 +00:00

proto

misc: Replace a deprecated method in protoio.cc.

2020-04-27 21:46:28 +00:00

python

base,misc: Added version to code

2020-04-22 19:50:39 +00:00

sim

sim, arch-arm: Restore capability of running without a kernel

2020-04-28 09:51:36 +00:00

systemc

misc: Replace __metaclass__ with six.add_metaclass

2020-03-10 09:35:56 +00:00

unittest

base,arch,sim,cpu: Move object file loader components into a namespace.

2020-04-22 06:08:54 +00:00

Doxyfile

misc: Updated Doxygen to state version as v19.0.0.0

2020-02-16 02:50:20 +00:00

SConscript

base,misc: Added version to code

2020-04-22 19:50:39 +00:00