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6d27a3bb502ac27b2837260cff65b294c8d3a8b8
gem5/src/cpu/minor
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Gabe Black 6d27a3bb50 cpu,arch: Turn the read|set*Operand methods into get/setRegOperand. 
This simplifies and generalizes the ExecContext interface significantly.
This does *not* change the "Writeable" accessors for the vec and pred
registers, and it also ignores MiscRegs which have some different
semantics.

Change-Id: I8cb80da890fc8915f03be04e136662a257d06946
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49114
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-19 20:23:51 +00:00
..
activity.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
activity.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
BaseMinorCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
buffers.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cpu.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
cpu.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
decode.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
decode.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
dyn_inst.cc
cpu: Stop using NumVecElemPerVecReg.
2022-02-01 18:47:17 +00:00
dyn_inst.hh
cpu-minor: Get rid of the MinorDynInst::init function.
2021-12-04 07:44:13 +00:00
exec_context.hh
cpu,arch: Turn the read|set*Operand methods into get/setRegOperand.
2022-02-19 20:23:51 +00:00
execute.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
execute.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
fetch1.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
fetch1.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
fetch2.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
fetch2.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
func_unit.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
func_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
lsq.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
lsq.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pipe_data.cc
cpu-minor: Convert the rest of the CPU to use PCStateBase *|&.
2021-11-23 07:45:29 +00:00
pipe_data.hh
cpu-minor: Ensure the pc in BranchData is always set.
2021-12-04 07:44:13 +00:00
pipeline.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
pipeline.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
SConscript
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
scoreboard.cc
cpu-minor: Fix for minor CPU scoreboard
2021-09-17 10:27:11 +00:00
scoreboard.hh
cpu: rename RegClass::size to RegClass::numRegs.
2022-02-04 12:11:59 +00:00
stats.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stats.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
trace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00