4fe56ff720
This simplifies the O3 CPU, and removes special cases around how vector registers are handled. Now ARM is responsible for maintaining its different register personalities internally. Also, this re-establishes the invariant that registers are indexed as complete, opaque entities with no internal structure, at least as far as the CPU is concerned. To make sure the KVM CPU sees the correct state, we need to sync over the vector registers if we're in 32 bit mode when moving state to or from gem5's ThreadContext. Change-Id: I36416d609310ae0bc50c18809f5d9e19bfbb4d37 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49147 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
152 lines
6.7 KiB
Python
152 lines
6.7 KiB
Python
# Copyright (c) 2012-2013, 2015-2021 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import SimObject
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from m5.objects.ArmPMU import ArmPMU
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from m5.objects.ArmSystem import SveVectorLength, ArmRelease
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from m5.objects.BaseISA import BaseISA
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# Enum for DecoderFlavor
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class DecoderFlavor(Enum): vals = ['Generic']
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class ArmDefaultSERelease(ArmRelease):
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extensions = [
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'CRYPTO',
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# Armv8.1
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'FEAT_LSE', 'FEAT_RDM',
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# Armv8.2
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'FEAT_SVE',
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# Armv8.3
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'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
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# Other
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'TME'
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]
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class ArmISA(BaseISA):
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type = 'ArmISA'
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cxx_class = 'gem5::ArmISA::ISA'
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cxx_header = "arch/arm/isa.hh"
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system = Param.System(Parent.any, "System this ISA object belongs to")
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pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
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decoderFlavor = Param.DecoderFlavor(
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'Generic', "Decoder flavor specification")
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release_se = Param.ArmRelease(ArmDefaultSERelease(),
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"Set of features/extensions to use in SE mode")
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# If no MIDR value is provided, 0x0 is treated by gem5 as follows:
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# When 'highest_el_is_64' (AArch64 support) is:
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# True -> Cortex-A57 TRM r0p0 MIDR is used
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# False -> Cortex-A15 TRM r0p0 MIDR is used
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midr = Param.UInt32(0x0, "MIDR value")
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# See section B4.1.89 - B4.1.92 of the ARM ARM
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# VMSAv7 support
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id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
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id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
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# no HW access | WFI stalling | ISB and DSB |
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# all TLB maintenance | no Harvard
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id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
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# SuperSec | Coherent TLB | Bcast Maint |
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# BP Maint | Cache Maint Set/way | Cache Maint MVA
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id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
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id_mmfr4 = Param.UInt32(0x00000000, "Memory Model Feature Register 4")
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# See section B4.1.84 of ARM ARM
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# All values are latest for ARMv7-A profile
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id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
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id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
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id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
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id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
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id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
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id_isar5 = Param.UInt32(0x11000000, "Instruction Set Attribute Register 5")
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# !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
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id_isar6 = Param.UInt32(0x00000001, "Instruction Set Attribute Register 6")
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fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
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# [31:0] is implementation defined
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id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
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"AArch64 Auxiliary Feature Register 0")
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# Reserved for future expansion
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id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
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"AArch64 Auxiliary Feature Register 1")
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# 1 CTX CMPs | 16 WRPs | 16 BRPs | !PMU | !Trace | Debug v8-A
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id_aa64dfr0_el1 = Param.UInt64(0x0000000000F0F006,
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"AArch64 Debug Feature Register 0")
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# Reserved for future expansion
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id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
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"AArch64 Debug Feature Register 1")
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# !FHM | !TME | !Atomic | !CRC32 | !SHA2 | RDM | !SHA1 | !AES
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id_aa64isar0_el1 = Param.UInt64(0x0000000010000000,
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"AArch64 Instruction Set Attribute Register 0")
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# !I8MM | !BF16 | SPECRES = 0 | !SB |
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# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
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id_aa64isar1_el1 = Param.UInt64(0x0000000001011010,
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"AArch64 Instruction Set Attribute Register 1")
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# 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
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id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
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"AArch64 Memory Model Feature Register 0")
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# PAN | HPDS | !VHE | VMIDBits
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id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101020,
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"AArch64 Memory Model Feature Register 1")
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# |VARANGE | UAO
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id_aa64mmfr2_el1 = Param.UInt64(0x0000000000010010,
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"AArch64 Memory Model Feature Register 2")
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# Any access (read/write) to an unimplemented
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# Implementation Defined registers is not causing an Undefined Instruction.
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# It is rather executed as a NOP.
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impdef_nop = Param.Bool(False,
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"Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP")
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# This is required because in SE mode a generic System SimObject is
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# allocated, instead of an ArmSystem
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sve_vl_se = Param.SveVectorLength(1,
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"SVE vector length in quadwords (128-bit), SE-mode only")
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# Recurse into subnodes to generate DTB entries. This is mainly needed to
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# generate the PMU entry.
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generateDeviceTree = SimObject.recurseDeviceTree
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