81c5ca17be
Change-Id: I3bac27ca8d5ed9fa11b519ea29b73c6d09260157 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34159 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
103 lines
3.5 KiB
C++
103 lines
3.5 KiB
C++
/*
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* Copyright (c) 2012, 2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARM_PROCESS_HH__
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#define __ARM_PROCESS_HH__
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#include <string>
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#include <vector>
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#include "arch/arm/intregs.hh"
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#include "base/loader/object_file.hh"
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#include "sim/syscall_abi.hh"
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class ArmProcess : public Process
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{
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protected:
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::Loader::Arch arch;
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ArmProcess(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile,
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::Loader::Arch _arch);
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template<class IntType>
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void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
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template<class IntType>
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IntType
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armHwcap() const
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{
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return static_cast<IntType>(armHwcapImpl());
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}
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/**
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* AT_HWCAP is 32-bit wide on AArch64 as well so we can
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* safely return an uint32_t */
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virtual uint32_t armHwcapImpl() const = 0;
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};
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class ArmProcess32 : public ArmProcess
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{
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public:
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ArmProcess32(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile,
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::Loader::Arch _arch);
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protected:
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void initState() override;
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/** AArch32 AT_HWCAP */
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uint32_t armHwcapImpl() const override;
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};
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class ArmProcess64 : public ArmProcess
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{
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public:
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ArmProcess64(const ProcessParams ¶ms, ::Loader::ObjectFile *objFile,
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::Loader::Arch _arch);
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protected:
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void initState() override;
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/** AArch64 AT_HWCAP */
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uint32_t armHwcapImpl() const override;
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};
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#endif // __ARM_PROCESS_HH__
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