Nilay Vaish 6a966d5eeb Ruby Sequencer: Schedule deadlock check event at correct time ...

The scheduling of the deadlock check event was being done incorrectly as the
clock was not being multiplied, so as to convert the time into ticks. This
patch removes that bug.

2012-05-22 11:32:57 -05:00

..

cache

Cache: restructure code that actually isn't a loop

2012-05-10 18:04:27 -05:00

config

Fixes to get prefetching working again.

2009-02-16 08:56:40 -08:00

protocol

MOESI_hammer: tbe allocation and dependent wakeup fixes

2012-04-06 13:47:07 -07:00

ruby

Ruby Sequencer: Schedule deadlock check event at correct time

2012-05-22 11:32:57 -05:00

slicc

clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6

2012-04-14 05:43:31 -04:00

abstract_mem.cc

gem5: assert before indexing intro arrays to verify bounds

2012-05-10 18:04:27 -05:00

abstract_mem.hh

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

AbstractMemory.py

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

bridge.cc

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

bridge.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

Bridge.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

bus.cc

MEM: Do not forward uncacheable to bus snoopers

2012-05-08 05:15:52 -04:00

bus.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

Bus.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

comm_monitor.cc

MEM: Add the communication monitor

2012-05-09 04:37:45 -04:00

comm_monitor.hh

MEM: Add the communication monitor

2012-05-09 04:37:45 -04:00

CommMonitor.py

MEM: Add the communication monitor

2012-05-09 04:37:45 -04:00

fs_translating_port_proxy.cc

mem: fix bug with CopyStringOut and null string termination.

2012-05-10 18:04:27 -05:00

fs_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

mem_object.cc

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

mem_object.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mport.cc

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

mport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet_queue.cc

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

packet_queue.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

packet.cc

MemCmd: Add a command for invalidation requests to LSQ

2012-01-23 11:07:11 -06:00

packet.hh

MEM: Remove the Broadcast destination from the packet

2012-04-14 05:45:55 -04:00

page_table.cc

Another merge with the main repository.

2012-01-07 02:16:37 -08:00

page_table.hh

SE/FS: Get rid of includes of config/full_system.hh.

2011-11-18 02:20:22 -08:00

physical.cc

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

physical.hh

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

port_proxy.cc

MEM: Remove the Broadcast destination from the packet

2012-04-14 05:45:55 -04:00

port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

port.cc

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

port.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

qport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

request.hh

mem: fix cache stats to use request ids correctly

2012-02-12 16:07:39 -06:00

SConscript

MEM: Add the communication monitor

2012-05-09 04:37:45 -04:00

se_translating_port_proxy.cc

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

se_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

simple_mem.cc

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

simple_mem.hh

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

SimpleMemory.py

MEM: Enable multiple distributed generalized memories

2012-04-06 13:46:31 -04:00

tport.cc

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

tport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00