Giacomo Travaglini 6995a99d77 arch-arm: TLBIs targeting EL2 regime are executable from S state ...

Those AArch64 instructions/registers were labelled as executable
from EL3 only if SCR_EL3.NS == 1. This is not valid anymore
after the introduction of FEAT_SEL2

Change-Id: Ie7b56f3fe779c3a99d4f0ef937c7c8ec0530b00e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2024-05-28 11:20:32 +01:00

..

amdgpu

arch-vega: Load/stores commonly used with 16b MFMA

2024-05-20 09:29:46 -05:00

arm

arch-arm: TLBIs targeting EL2 regime are executable from S state

2024-05-28 11:20:32 +01:00

generic

arch-generic: Avoid out-of-memory errors for bad semihosting calls (#1143)

2024-05-16 10:28:10 -07:00

isa_parser

arch: Fix inst flag of RISC-V vector store macro instructions

2023-12-12 17:04:31 +08:00

mips

misc: Serialize the ISA as a string in the checkpoint

2024-03-04 17:51:40 +00:00

null

scons: Update the Kconfig build options

2023-11-23 08:26:11 +08:00

power

misc: Serialize the ISA as a string in the checkpoint

2024-03-04 17:51:40 +00:00

riscv

arch-riscv: Fix c.jalr and c.jr instruction (#1163)

2024-05-25 20:18:42 -07:00

sparc

arch-riscv,sim: m5ops argument / return fix for 32 bit RISC-V (#900)

2024-04-08 10:09:17 -07:00

x86

arch-x86: Improve KVM set XCR (#1138)

2024-05-20 10:22:48 -07:00

Kconfig

scons: Update the Kconfig build options

2023-11-23 08:26:11 +08:00

micro_asm_test.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

micro_asm.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

SConscript

arch-gcn3: Remove all GCN3 files

2024-01-17 10:44:44 -06:00