Giacomo Travaglini 683007c6ca arch-arm: Add FEAT_FGT Debug Read/Write registers ...

Those are supposed to control trapping for accesses to debug registers

Change-Id: I4a25a379e718ea6d5ea8ae22ac7edbeb452d1836
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>

2024-02-15 15:58:34 +00:00

..

arch

arch-arm: Add FEAT_FGT Debug Read/Write registers

2024-02-15 15:58:34 +00:00

base

base: Add a check for edge case

2024-01-23 11:35:54 -08:00

cpu

cpu-o3: add PerThreadUnifiedThreadMap to O3 CPU (#842)

2024-02-12 09:26:31 -08:00

dev

dev: Fix off-by-one in IDE controller PCI register allocation (#824)

2024-02-01 10:14:28 -08:00

doc

…

doxygen

…

gpu-compute

gpu-compute: Remove unused and redundant functions

2024-02-09 12:17:24 -06:00

kern

misc: Fix 'maybe-uninitialized' warn turn off (#706)

2023-12-21 18:45:56 -08:00

learning_gem5

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mem

gpu-compute, mem-ruby: Add comments and reformat code

2024-02-09 12:17:24 -06:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

stdlib: fix typo in error message (#855)

2024-02-06 09:50:01 -08:00

sim

sim: Updating Process::Map (#835)

2024-02-05 12:17:05 -08:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: Reduce unnecessary backdoor request in atomic transaction (#795)

2024-02-05 11:08:20 -08:00

Doxyfile

misc: Change version information to develop for v24.0

2023-12-27 12:29:52 -08:00

Kconfig

scons: Add new config option HAVE_CAPSTONE to Kconfig

2023-11-23 08:26:11 +08:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00