Andreas Sandberg 672953ef43 cpu: Support trace termination in BaseTrafficGen ...

Make the BaseTrafficGen handle cases where getNextPacket() can't find
a new packet and returns NULL. In that case, assume the generator has
run out of packets and switch to the next generator.

Change-Id: I5ca6ead550005812fb849ed9ce6b5007a65ddfa7
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11517
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

2018-07-13 09:26:23 +00:00

..

arch

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

base

base: Add a M5_PUBLIC and M5_LOCAL attribute macro

2018-06-29 08:50:42 +00:00

cpu

cpu: Support trace termination in BaseTrafficGen

2018-07-13 09:26:23 +00:00

dev

dev-arm: Use recurseDeviceTree instead of custom in platform

2018-06-21 14:21:44 +00:00

doc

docs: Fix power model doxygen

2018-04-20 15:59:35 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

gpu-compute: Remove unneeded Request::setVirt call

2018-06-26 16:46:40 +00:00

kern

sim-se: Add /sys/devices/system/cpu/online file

2018-03-15 20:45:34 +00:00

learning_gem5

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

mem

mem: Add a memory delay simulator

2018-06-28 16:12:53 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

python: Fix call bug in @cxxMethod when override is True

2018-06-28 17:40:26 +00:00

sim

syscall_emul: adding symlink system call

2018-06-25 20:42:30 +00:00

unittest

base, mem: Disambiguate if an addr range is contained or overlaps

2018-06-19 14:24:25 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Generalize building binaries.

2018-06-26 00:15:12 +00:00