Gabe Black 63ac86ecbb arch: Add a virtual destructor to BaseHTMCheckpoint. ...

Since it has virtual methods, it should also have a virtual destructor.
My compiler complains otherwise, which breaks my build.

Change-Id: I44bba97b76931bab6e3511fcdee79831080c12d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34215
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-09-09 07:08:53 +00:00

..

arm

arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.

2020-09-08 23:57:56 +00:00

gcn3

arch-gcn3: Update LmReqsInPipe in atomic flats when execMask=0

2020-08-27 20:46:28 +00:00

generic

arch: Add a virtual destructor to BaseHTMCheckpoint.

2020-09-09 07:08:53 +00:00

mips

base, sim: Make ByteOrder into a ScopedEnum accessible to Python

2020-09-08 16:24:00 +00:00

null

arch: Don't add contents to the TheISA namespace in arch/generic.

2020-08-20 01:36:24 +00:00

power

base, sim: Make ByteOrder into a ScopedEnum accessible to Python

2020-09-08 16:24:00 +00:00

riscv

base, sim: Make ByteOrder into a ScopedEnum accessible to Python

2020-09-08 16:24:00 +00:00

sparc

base, sim: Make ByteOrder into a ScopedEnum accessible to Python

2020-09-08 16:24:00 +00:00

x86

base, sim: Make ByteOrder into a ScopedEnum accessible to Python

2020-09-08 16:24:00 +00:00

isa_parser.py

arch: list.sort() sorting by key only in python3

2020-03-13 14:24:07 +00:00

micro_asm_test.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

micro_asm.py

misc: Make exception handling python3 compliant

2020-03-13 14:24:07 +00:00

SConscript

arch,cpu,sim: Get rid of the microcode ROM stub code.

2020-08-25 12:41:30 +00:00