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arch-gcn3: Update LmReqsInPipe in atomic flats when execMask=0

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In flat instructions, wrLmReqsInPipe/rdLmReqsInPipe are decremented
in the calcAddr() function. However, the calcAddr() function is only
called when execMask != 0.

This patch adds in statements to decrement wrLmReqsInPipe and
rdLmReqsInPipe in all implemented atomic flats when execMask is 0.

This fixes a scenario where vector local memory and flat instructions
are unable to execute due to LocalMemPipeline::isLMReqFIFOWrRdy
always returning false in ScheduleStage::dispatchReady after too many
atomic flats execute with execMask = 0

Change-Id: I081cfd3faf74bbfcf0728445e7160fa2a76a6a7e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32614
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Kyle Roarty
2020-08-12 18:08:05 -05:00
parent 52f392b947
commit 0983929a24
1 changed files with 22 additions and 0 deletions
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22
src/arch/gcn3/insts/instructions.cc
View File

@@ -40374,6 +40374,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -40481,6 +40483,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -40589,6 +40593,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -40684,6 +40690,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -40953,6 +40961,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -41048,6 +41058,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -41172,6 +41184,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -41281,6 +41295,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -41378,6 +41394,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -41657,6 +41675,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->
@@ -41755,6 +41775,8 @@ namespace Gcn3ISA
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
wf->wrLmReqsInPipe--;
wf->rdLmReqsInPipe--;
if (instData.GLC) {
gpuDynInst->exec_mask = wf->execMask();
wf->computeUnit->vrf[wf->simdId]->