614b608a08
The example reset controller provides a register interface to config RVBAR and ability to reset the core. Change-Id: I088ddde6f44ff9cc5914afb834ec07a8f7f269fa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54065 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
137 lines
4.2 KiB
C++
137 lines
4.2 KiB
C++
/*
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* Copyright 2021 Google, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/arm/fastmodel/reset_controller/example.hh"
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#include <algorithm>
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#include "base/logging.hh"
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namespace gem5
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{
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namespace fastmodel
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{
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ResetControllerExample::CorePins::CorePins(const std::string &module_name)
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: reset(module_name + ".reset", 0, this),
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halt(module_name + ".halt", 0, this)
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{}
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ResetControllerExample::Registers::Registers(
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const std::string &module_name, Iris::BaseCPU *c, CorePins *p)
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: RegisterBankLE(module_name, 0), cpu(c), pins(p),
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nsrvbar(module_name + ".nsrvbar"),
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rvbar(module_name + ".rvbar"),
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reset(module_name + ".reset"),
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halt(module_name + ".halt")
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{
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panic_if(cpu == nullptr, "ResetControllerExample needs a target cpu.");
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nsrvbar.writer(
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[this] (auto ®, auto val)
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{
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cpu->setResetAddr(val, false);
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});
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rvbar.writer(
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[this] (auto ®, auto val)
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{
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cpu->setResetAddr(val, true);
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});
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reset.writer(
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[this] (auto ®, auto val)
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{
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panic_if(!pins->reset.isConnected(),
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"%s is not connected.", pins->reset.name());
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if (val)
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pins->reset.raise();
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else
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pins->reset.lower();
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});
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halt.writer(
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[this] (auto ®, auto val)
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{
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panic_if(!pins->halt.isConnected(),
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"%s is not connected.", pins->halt.name());
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if (val)
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pins->halt.raise();
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else
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pins->halt.lower();
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});
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addRegisters({
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nsrvbar,
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rvbar,
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reset,
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halt,
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});
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}
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ResetControllerExample::ResetControllerExample(const Params &p)
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: BasicPioDevice(p, 0x20),
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pins(p.name + ".pins"),
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registers(p.name + ".registers", p.cpu, &pins)
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{}
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Tick
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ResetControllerExample::read(PacketPtr pkt)
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{
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pkt->makeResponse();
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auto data = pkt->getPtr<uint8_t>();
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auto size = pkt->getSize();
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std::fill(data, data + size, 0);
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return pioDelay;
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}
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Tick
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ResetControllerExample::write(PacketPtr pkt)
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{
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pkt->makeResponse();
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size_t size = pkt->getSize();
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if (size != 4 && size != 8) {
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pkt->setBadAddress();
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} else {
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auto addr = pkt->getAddr() - pioAddr;
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registers.write(addr, pkt->getPtr<void>(), size);
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}
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return pioDelay;
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}
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Port &
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ResetControllerExample::getPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "reset")
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return pins.reset;
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else if (if_name == "halt")
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return pins.halt;
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return BasicPioDevice::getPort(if_name, idx);
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}
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} // namespace fastmodel
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} // namespace gem5
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