Commit Graph

1 Commits

Author SHA1 Message Date
Yu-hsin Wang
614b608a08 fastmodel: Add an example reset controller for IrisCpu
The example reset controller provides a register interface to config
RVBAR and ability to reset the core.

Change-Id: I088ddde6f44ff9cc5914afb834ec07a8f7f269fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54065
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-11 02:11:40 +00:00