5df96cb690
This patch cleans up the packet memory allocation confusion. The data is always allocated at the requesting side, when a packet is created (or copied), and there is never a need for any device to allocate any space if it is merely responding to a paket. This behaviour is in line with how SystemC and TLM works as well, thus increasing interoperability, and matching established conventions. The redundant calls to Packet::allocate are removed, and the checks in the function are tightened up to make sure data is only ever allocated once. There are still some oddities in the packet copy constructor where we copy the data pointer if it is static (without ownership), and allocate new space if the data is dynamic (with ownership). The latter is being worked on further in a follow-on patch.
334 lines
9.2 KiB
C++
334 lines
9.2 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#include "base/trace.hh"
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#include "debug/Checkpoint.hh"
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#include "debug/Uart.hh"
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#include "dev/arm/amba_device.hh"
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#include "dev/arm/base_gic.hh"
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#include "dev/arm/pl011.hh"
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#include "dev/terminal.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/sim_exit.hh"
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Pl011::Pl011(const Params *p)
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: Uart(p, 0xfff), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
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imsc(0), rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic),
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endOnEOT(p->end_on_eot), intDelay(p->int_delay), intEvent(this)
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{
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}
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Tick
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Pl011::read(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
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// use a temporary data since the uart registers are read/written with
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// different size operations
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//
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uint32_t data = 0;
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switch(daddr) {
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case UART_DR:
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data = 0;
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if (term->dataAvailable())
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data = term->in();
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break;
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case UART_FR:
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// For now we're infintely fast, so TX is never full, always empty,
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// always clear to send
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data = UART_FR_TXFE | UART_FR_CTS;
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if (!term->dataAvailable())
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data |= UART_FR_RXFE;
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DPRINTF(Uart, "Reading FR register as %#x rawInt=0x%x imsc=0x%x maskInt=0x%x\n",
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data, rawInt, imsc, maskInt);
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break;
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case UART_CR:
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data = control;
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break;
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case UART_IBRD:
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data = ibrd;
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break;
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case UART_FBRD:
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data = fbrd;
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break;
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case UART_LCRH:
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data = lcrh;
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break;
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case UART_IFLS:
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data = ifls;
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break;
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case UART_IMSC:
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data = imsc;
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break;
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case UART_RIS:
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data = rawInt;
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DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
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break;
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case UART_MIS:
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DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", rawInt);
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data = maskInt;
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break;
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default:
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if (readId(pkt, AMBA_ID, pioAddr)) {
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// Hack for variable size accesses
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data = pkt->get<uint32_t>();
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break;
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}
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panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
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break;
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}
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switch(pkt->getSize()) {
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case 1:
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pkt->set<uint8_t>(data);
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break;
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case 2:
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pkt->set<uint16_t>(data);
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break;
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case 4:
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pkt->set<uint32_t>(data);
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break;
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default:
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panic("Uart read size too big?\n");
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break;
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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Pl011::write(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
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pkt->get<uint8_t>(), pkt->getSize());
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// use a temporary data since the uart registers are read/written with
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// different size operations
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//
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uint32_t data = 0;
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switch(pkt->getSize()) {
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case 1:
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data = pkt->get<uint8_t>();
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break;
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case 2:
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data = pkt->get<uint16_t>();
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break;
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case 4:
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data = pkt->get<uint32_t>();
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break;
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default:
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panic("Uart write size too big?\n");
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break;
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}
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switch (daddr) {
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case UART_DR:
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if ((data & 0xFF) == 0x04 && endOnEOT)
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exitSimLoop("UART received EOT", 0);
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term->out(data & 0xFF);
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//raw interrupt is set regardless of imsc.txim
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rawInt.txim = 1;
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if (imsc.txim) {
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DPRINTF(Uart, "TX int enabled, scheduling interruptt\n");
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if (!intEvent.scheduled())
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schedule(intEvent, curTick() + intDelay);
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}
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break;
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case UART_CR:
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control = data;
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break;
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case UART_IBRD:
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ibrd = data;
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break;
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case UART_FBRD:
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fbrd = data;
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break;
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case UART_LCRH:
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lcrh = data;
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break;
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case UART_IFLS:
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ifls = data;
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break;
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case UART_IMSC:
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imsc = data;
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if (imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd)
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panic("Unknown interrupt enabled\n");
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// rimim, ctsmim, dcdmim, dsrmim can be enabled but are ignored
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// they are supposed to interrupt on a change of status in the line
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// which we should never have since our terminal is happy to always
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// receive bytes.
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if (imsc.txim) {
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DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n");
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rawInt.txim = 1;
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if (!intEvent.scheduled())
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schedule(intEvent, curTick() + intDelay);
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}
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break;
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case UART_ICR:
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DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
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rawInt = rawInt & ~data;
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maskInt = rawInt & imsc;
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DPRINTF(Uart, " -- Masked interrupts 0x%x\n", maskInt);
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if (!maskInt)
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gic->clearInt(intNum);
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break;
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default:
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panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
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break;
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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void
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Pl011::dataAvailable()
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{
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/*@todo ignore the fifo, just say we have data now
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* We might want to fix this, or we might not care */
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rawInt.rxim = 1;
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rawInt.rtim = 1;
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DPRINTF(Uart, "Data available, scheduling interrupt\n");
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if (!intEvent.scheduled())
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schedule(intEvent, curTick() + intDelay);
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}
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void
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Pl011::generateInterrupt()
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{
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DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
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imsc, rawInt, maskInt);
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maskInt = imsc & rawInt;
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if (maskInt.rxim || maskInt.rtim || maskInt.txim) {
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gic->sendInt(intNum);
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DPRINTF(Uart, " -- Generated\n");
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}
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}
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void
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Pl011::serialize(std::ostream &os)
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{
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DPRINTF(Checkpoint, "Serializing Arm PL011\n");
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SERIALIZE_SCALAR(control);
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SERIALIZE_SCALAR(fbrd);
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SERIALIZE_SCALAR(ibrd);
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SERIALIZE_SCALAR(lcrh);
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SERIALIZE_SCALAR(ifls);
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uint16_t imsc_serial = imsc;
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SERIALIZE_SCALAR(imsc_serial);
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uint16_t rawInt_serial = rawInt;
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SERIALIZE_SCALAR(rawInt_serial);
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uint16_t maskInt_serial = maskInt;
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SERIALIZE_SCALAR(maskInt_serial);
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SERIALIZE_SCALAR(endOnEOT);
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SERIALIZE_SCALAR(intDelay);
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}
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void
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Pl011::unserialize(Checkpoint *cp, const std::string §ion)
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{
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DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
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UNSERIALIZE_SCALAR(control);
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UNSERIALIZE_SCALAR(fbrd);
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UNSERIALIZE_SCALAR(ibrd);
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UNSERIALIZE_SCALAR(lcrh);
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UNSERIALIZE_SCALAR(ifls);
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uint16_t imsc_serial;
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UNSERIALIZE_SCALAR(imsc_serial);
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imsc = imsc_serial;
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uint16_t rawInt_serial;
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UNSERIALIZE_SCALAR(rawInt_serial);
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rawInt = rawInt_serial;
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uint16_t maskInt_serial;
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UNSERIALIZE_SCALAR(maskInt_serial);
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maskInt = maskInt_serial;
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UNSERIALIZE_SCALAR(endOnEOT);
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UNSERIALIZE_SCALAR(intDelay);
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}
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Pl011 *
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Pl011Params::create()
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{
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return new Pl011(this);
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}
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