167cf86375
Rather than having two separate MiscReg metadata vectors, we are storing the access permission bitset within the MiscRegLUTEntry Change-Id: I2f5d175617c888f0eb6954d29a4c607e0cbc3611 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61674 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
536 lines
18 KiB
C++
536 lines
18 KiB
C++
/*
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* Copyright (c) 2010, 2012-2021 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_ISA_HH__
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#define __ARCH_ARM_ISA_HH__
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#include "arch/arm/isa_device.hh"
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#include "arch/arm/mmu.hh"
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#include "arch/arm/pcstate.hh"
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#include "arch/arm/regs/int.hh"
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#include "arch/arm/regs/misc.hh"
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#include "arch/arm/self_debug.hh"
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#include "arch/arm/system.hh"
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#include "arch/arm/types.hh"
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#include "arch/arm/utility.hh"
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#include "arch/generic/isa.hh"
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#include "debug/Checkpoint.hh"
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#include "enums/DecoderFlavor.hh"
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#include "sim/sim_object.hh"
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namespace gem5
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{
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struct ArmISAParams;
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struct DummyArmISADeviceParams;
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class Checkpoint;
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class EventManager;
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namespace ArmISA
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{
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class ISA : public BaseISA
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{
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protected:
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// Parent system
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ArmSystem *system;
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// Micro Architecture
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const enums::DecoderFlavor _decoderFlavor;
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/** Dummy device for to handle non-existing ISA devices */
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DummyISADevice dummyDevice;
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// PMU belonging to this ISA
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BaseISADevice *pmu;
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// Generic timer interface belonging to this ISA
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std::unique_ptr<BaseISADevice> timer;
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// GICv3 CPU interface belonging to this ISA
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std::unique_ptr<BaseISADevice> gicv3CpuInterface;
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// Cached copies of system-level properties
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bool highestELIs64;
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bool haveLargeAsid64;
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uint8_t physAddrRange;
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/** SVE vector length in quadwords */
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unsigned sveVL;
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/** This could be either a FS or a SE release */
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const ArmRelease *release;
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/**
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* If true, accesses to IMPLEMENTATION DEFINED registers are treated
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* as NOP hence not causing UNDEFINED INSTRUCTION.
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*/
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bool impdefAsNop;
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bool afterStartup;
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SelfDebug * selfDebug;
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const MiscRegLUTEntryInitializer
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InitReg(uint32_t reg)
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{
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return MiscRegLUTEntryInitializer(lookUpMiscReg[reg]);
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}
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void initializeMiscRegMetadata();
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RegVal miscRegs[NUM_MISCREGS];
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const RegId *intRegMap;
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void
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updateRegMap(CPSR cpsr)
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{
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if (cpsr.width == 0) {
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intRegMap = int_reg::Reg64Map;
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} else {
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switch (cpsr.mode) {
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case MODE_USER:
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case MODE_SYSTEM:
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intRegMap = int_reg::RegUsrMap;
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break;
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case MODE_FIQ:
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intRegMap = int_reg::RegFiqMap;
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break;
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case MODE_IRQ:
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intRegMap = int_reg::RegIrqMap;
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break;
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case MODE_SVC:
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intRegMap = int_reg::RegSvcMap;
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break;
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case MODE_MON:
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intRegMap = int_reg::RegMonMap;
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break;
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case MODE_ABORT:
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intRegMap = int_reg::RegAbtMap;
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break;
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case MODE_HYP:
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intRegMap = int_reg::RegHypMap;
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break;
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case MODE_UNDEFINED:
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intRegMap = int_reg::RegUndMap;
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break;
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default:
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panic("Unrecognized mode setting in CPSR.\n");
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}
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}
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}
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BaseISADevice &getGenericTimer();
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BaseISADevice &getGICv3CPUInterface();
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public:
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void clear();
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protected:
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void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
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void clear64(const ArmISAParams &p);
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void initID32(const ArmISAParams &p);
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void initID64(const ArmISAParams &p);
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void addressTranslation(MMU::ArmTranslationType tran_type,
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BaseMMU::Mode mode, Request::Flags flags, RegVal val);
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void addressTranslation64(MMU::ArmTranslationType tran_type,
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BaseMMU::Mode mode, Request::Flags flags, RegVal val);
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public:
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SelfDebug*
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getSelfDebug() const
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{
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return selfDebug;
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}
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static SelfDebug*
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getSelfDebug(ThreadContext *tc)
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{
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auto *arm_isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
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return arm_isa->getSelfDebug();
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}
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const ArmRelease* getRelease() const { return release; }
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RegVal readMiscRegNoEffect(int misc_reg) const;
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RegVal readMiscReg(int misc_reg);
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void setMiscRegNoEffect(int misc_reg, RegVal val);
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void setMiscReg(int misc_reg, RegVal val);
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RegId
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flattenRegId(const RegId& regId) const
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{
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switch (regId.classValue()) {
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case IntRegClass:
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return intRegClass[flattenIntIndex(regId.index())];
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case FloatRegClass:
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panic("ARM doesn't use FloatRegClass.");
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case VecRegClass:
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return vecRegClass[flattenVecIndex(regId.index())];
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case VecElemClass:
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return vecElemClass[flattenVecElemIndex(regId.index())];
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case VecPredRegClass:
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return vecPredRegClass[flattenVecPredIndex(regId.index())];
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case CCRegClass:
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return ccRegClass[flattenCCIndex(regId.index())];
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case MiscRegClass:
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return miscRegClass[flattenMiscIndex(regId.index())];
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case InvalidRegClass:
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return RegId();
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}
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panic("Unrecognized register class %d.", regId.classValue());
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}
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int
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flattenIntIndex(int reg) const
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{
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assert(reg >= 0);
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if (reg < int_reg::NumArchRegs) {
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return intRegMap[reg];
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} else if (reg < int_reg::NumRegs) {
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return reg;
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} else if (reg == int_reg::Spx) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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ExceptionLevel el = opModeToEL(
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(OperatingMode) (uint8_t) cpsr.mode);
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if (!cpsr.sp && el != EL0)
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return int_reg::Sp0;
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switch (el) {
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case EL3:
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return int_reg::Sp3;
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case EL2:
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return int_reg::Sp2;
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case EL1:
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return int_reg::Sp1;
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case EL0:
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return int_reg::Sp0;
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default:
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panic("Invalid exception level");
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return 0; // Never happens.
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}
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} else {
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return flattenIntRegModeIndex(reg);
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}
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}
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int
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flattenFloatIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenVecIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenVecElemIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenVecPredIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenCCIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenMiscIndex(int reg) const
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{
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assert(reg >= 0);
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int flat_idx = reg;
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if (reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_EL0T:
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warn("User mode does not have SPSR\n");
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flat_idx = MISCREG_SPSR;
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break;
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case MODE_EL1T:
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case MODE_EL1H:
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flat_idx = MISCREG_SPSR_EL1;
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break;
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case MODE_EL2T:
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case MODE_EL2H:
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flat_idx = MISCREG_SPSR_EL2;
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break;
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case MODE_EL3T:
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case MODE_EL3H:
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flat_idx = MISCREG_SPSR_EL3;
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break;
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case MODE_USER:
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warn("User mode does not have SPSR\n");
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flat_idx = MISCREG_SPSR;
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break;
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case MODE_FIQ:
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flat_idx = MISCREG_SPSR_FIQ;
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break;
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case MODE_IRQ:
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flat_idx = MISCREG_SPSR_IRQ;
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break;
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case MODE_SVC:
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flat_idx = MISCREG_SPSR_SVC;
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break;
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case MODE_MON:
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flat_idx = MISCREG_SPSR_MON;
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break;
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case MODE_ABORT:
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flat_idx = MISCREG_SPSR_ABT;
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break;
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case MODE_HYP:
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flat_idx = MISCREG_SPSR_HYP;
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break;
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case MODE_UNDEFINED:
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flat_idx = MISCREG_SPSR_UND;
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break;
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default:
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warn("Trying to access SPSR in an invalid mode: %d\n",
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cpsr.mode);
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flat_idx = MISCREG_SPSR;
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break;
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}
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} else if (lookUpMiscReg[reg].info[MISCREG_MUTEX]) {
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// Mutually exclusive CP15 register
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switch (reg) {
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case MISCREG_PRRR_MAIR0:
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case MISCREG_PRRR_MAIR0_NS:
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case MISCREG_PRRR_MAIR0_S:
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{
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TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
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// If the muxed reg has been flattened, work out the
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// offset and apply it to the unmuxed reg
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int idxOffset = reg - MISCREG_PRRR_MAIR0;
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if (ttbcr.eae)
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flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
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idxOffset);
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else
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flat_idx = flattenMiscIndex(MISCREG_PRRR +
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idxOffset);
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}
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break;
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case MISCREG_NMRR_MAIR1:
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case MISCREG_NMRR_MAIR1_NS:
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case MISCREG_NMRR_MAIR1_S:
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{
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TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
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// If the muxed reg has been flattened, work out the
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// offset and apply it to the unmuxed reg
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int idxOffset = reg - MISCREG_NMRR_MAIR1;
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if (ttbcr.eae)
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flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
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idxOffset);
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else
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flat_idx = flattenMiscIndex(MISCREG_NMRR +
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idxOffset);
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}
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break;
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case MISCREG_PMXEVTYPER_PMCCFILTR:
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{
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PMSELR pmselr = miscRegs[MISCREG_PMSELR];
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if (pmselr.sel == 31)
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flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR);
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else
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flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER);
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}
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break;
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default:
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panic("Unrecognized misc. register.\n");
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break;
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}
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} else {
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if (lookUpMiscReg[reg].info[MISCREG_BANKED]) {
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bool secure_reg = !highestELIs64 && inSecureState();
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flat_idx += secure_reg ? 2 : 1;
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} else {
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flat_idx = snsBankedIndex64((MiscRegIndex)reg,
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!inSecureState());
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}
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}
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return flat_idx;
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}
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/**
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* Returns the enconcing equivalent when VHE is implemented and
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* HCR_EL2.E2H is enabled and executing at EL2
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*/
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int redirectRegVHE(int misc_reg);
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int
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snsBankedIndex64(MiscRegIndex reg, bool ns) const
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{
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int reg_as_int = static_cast<int>(reg);
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if (lookUpMiscReg[reg].info[MISCREG_BANKED64]) {
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reg_as_int += (release->has(ArmExtension::SECURITY) && !ns) ?
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2 : 1;
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}
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return reg_as_int;
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}
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std::pair<int,int>
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getMiscIndices(int misc_reg) const
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{
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// Note: indexes of AArch64 registers are left unchanged
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int flat_idx = flattenMiscIndex(misc_reg);
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if (lookUpMiscReg[flat_idx].lower == 0) {
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return std::make_pair(flat_idx, 0);
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}
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// do additional S/NS flattenings if mapped to NS while in S
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bool S = !highestELIs64 && inSecureState();
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int lower = lookUpMiscReg[flat_idx].lower;
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int upper = lookUpMiscReg[flat_idx].upper;
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// upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
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lower += S && lookUpMiscReg[lower].info[MISCREG_BANKED_CHILD];
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upper += S && lookUpMiscReg[upper].info[MISCREG_BANKED_CHILD];
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return std::make_pair(lower, upper);
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}
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/** Return true if the PE is in Secure state */
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bool inSecureState() const;
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/**
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* Returns the current Exception Level (EL) of the ISA object
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*/
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ExceptionLevel currEL() const;
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unsigned getCurSveVecLenInBits() const;
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unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; }
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template <typename Elem>
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static void
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zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
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{
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static_assert(sizeof(Elem) <= sizeof(uint64_t),
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"Elem type is too large.");
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eCount *= (sizeof(uint64_t) / sizeof(Elem));
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for (int i = 16 / sizeof(Elem); i < eCount; ++i) {
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v[i] = 0;
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}
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}
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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void startup() override;
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void setupThreadContext();
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PCStateBase *
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newPCState(Addr new_inst_addr=0) const override
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{
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return new PCState(new_inst_addr);
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}
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void takeOverFrom(ThreadContext *new_tc,
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ThreadContext *old_tc) override;
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enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
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/** Returns true if the ISA has a GICv3 cpu interface */
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bool
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haveGICv3CpuIfc() const
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{
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// gicv3CpuInterface is initialized at startup time, hence
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// trying to read its value before the startup stage will lead
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// to an error
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assert(afterStartup);
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return gicv3CpuInterface != nullptr;
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}
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PARAMS(ArmISA);
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ISA(const Params &p);
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uint64_t
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getExecutingAsid() const override
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{
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return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
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}
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bool
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inUserMode() const override
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{
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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return ArmISA::inUserMode(cpsr);
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}
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void copyRegsFrom(ThreadContext *src) override;
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void handleLockedRead(const RequestPtr &req) override;
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void handleLockedRead(ExecContext *xc, const RequestPtr &req) override;
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bool handleLockedWrite(const RequestPtr &req,
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Addr cacheBlockMask) override;
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bool handleLockedWrite(ExecContext *xc, const RequestPtr &req,
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Addr cacheBlockMask) override;
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void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override;
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void handleLockedSnoop(ExecContext *xc, PacketPtr pkt,
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Addr cacheBlockMask) override;
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void handleLockedSnoopHit() override;
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void handleLockedSnoopHit(ExecContext *xc) override;
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void globalClearExclusive() override;
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void globalClearExclusive(ExecContext *xc) override;
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};
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} // namespace ArmISA
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} // namespace gem5
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#endif
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