gem5/src/arch/sparc at 537239b278f7b8171d2eb09ef7f99c332266c48f - gem5

isa

SPARC: Make nops have the IsNop flag set.

2007-08-13 16:11:27 -07:00

linux

Ignore "time" and "times" syscalls.

2007-03-20 23:53:52 -04:00

solaris

Implement current working directory for LiveProcesses

2006-11-16 12:43:11 -08:00

asi.cc

Panic if any CMT registers are accessed

2007-03-08 21:49:13 -05:00

asi.hh

Panic if any CMT registers are accessed

2007-03-08 21:49:13 -05:00

faults.cc

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

faults.hh

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

floatregfile.cc

fix mostly floating point related

2007-02-02 18:04:42 -05:00

floatregfile.hh

Moved some constants from isa_traits.hh to the reg file headers.

2006-11-22 23:49:44 -05:00

handlers.hh

SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault ASI accesses work.

2007-08-13 16:02:47 -07:00

interrupts.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

intregfile.cc

Make SPARC checkpointing work

2007-01-30 18:25:39 -05:00

intregfile.hh

Fixed an off-by-one error.

2007-03-08 00:55:16 -05:00

isa_traits.hh

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

kernel_stats.hh

Put kernel_stats back into arch.

2006-11-07 22:34:34 -05:00

locked_mem.hh

Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)

2006-10-08 10:53:24 -07:00

miscregfile.cc

SPARC: Move tlb state into the tlb.

2007-08-13 16:06:50 -07:00

miscregfile.hh

SPARC: Move tlb state into the tlb.

2007-08-13 16:06:50 -07:00

mmaped_ipr.hh

reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes)

2006-12-04 19:39:57 -05:00

pagetable.cc

Make SPARC checkpointing work

2007-01-30 18:25:39 -05:00

pagetable.hh

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00

predecoder.hh

Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.

2007-06-19 18:17:34 +00:00

process.cc

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

process.hh

Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.

2007-02-28 16:36:38 +00:00

regfile.cc

SPARC: Move tlb state into the tlb.

2007-08-13 16:06:50 -07:00

regfile.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

remote_gdb.cc

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

remote_gdb.hh

Fix up the remote gdb include gaurds so it doesn't use the same symbol as Alpha does.

2007-03-05 14:46:49 +00:00

SConscript

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

SConsopts

Rework the way SCons recurses into subdirectories, making it

2007-03-10 23:00:54 -08:00

sparc_traits.hh

Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used.

2007-04-22 17:43:45 +00:00

SparcSystem.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

SparcTLB.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

stacktrace.cc

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

stacktrace.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

syscallreturn.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

system.cc

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

system.hh

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

tlb_map.hh

fix smul and sdiv to sign extend, and handle overflow/underflow corretly

2007-01-25 13:43:46 -05:00

tlb.cc

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

tlb.hh

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

types.hh

Make register indexes larger so they can actually hold all the legal values. Oops!

2007-04-14 17:08:24 +00:00

ua2005.cc

fix interrupting during a quisce on sparc

2007-03-13 00:05:52 -04:00

utility.cc

Arguments: Get rid of duplicate code for the Arguments class in each architecture.

2007-08-01 16:59:14 -04:00

utility.hh

Arguments: Get rid of duplicate code for the Arguments class in each architecture.

2007-08-01 16:59:14 -04:00

vtophys.cc

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

vtophys.hh

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00