Andreas Sandberg 694005b536 arch-arm: Use named constants for m5op instructions ...

Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4263
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

2017-08-01 18:27:06 +00:00

..

alpha

arch: ISA parser additions of vector registers

2017-07-05 14:43:49 +00:00

arm

arch-arm: Use named constants for m5op instructions

2017-08-01 18:27:06 +00:00

generic

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

hsail

base, sim, arch: Fix clang 5.0 warnings

2017-05-19 08:00:45 +00:00

mips

mips, x86: Refactor some Event subclasses into lambdas

2017-07-12 20:07:05 +00:00

null

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

power

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

riscv

riscv: Define register index constants using literals

2017-07-17 14:59:58 +00:00

sparc

arch: ISA parser additions of vector registers

2017-07-05 14:43:49 +00:00

x86

sim, x86: Make clone a virtual function

2017-07-17 15:16:32 +00:00

isa_parser.py

arch: ISA parser additions of vector registers

2017-07-05 14:43:49 +00:00

micro_asm_test.py

…

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00