Pouya Fotouhi 512da27dc9 mem-ruby: Remove assertion with incorrect assumption ...

Current code assumes that only one cacheline would either be in
RW. This is not true for GPU protocols, and may not be true
for some CPU-only protocols with state violations.

Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-08-02 18:31:12 +00:00

..

CacheRecorder.cc

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

CacheRecorder.hh

mem: Standardize mem folder header guards

2018-02-06 10:26:27 +00:00

DMASequencer.cc

ruby: fix typo in DMASequencer::ackCallback()

2016-12-20 11:53:36 -05:00

DMASequencer.hh

ruby: Allow multiple outstanding DMA requests

2016-10-26 22:48:37 -04:00

GPUCoalescer.cc

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

2019-05-18 10:20:20 +00:00

GPUCoalescer.hh

mem-ruby: Hit latencies defined by the controllers

2019-05-14 22:01:12 +00:00

GPUCoalescer.py

mem-ruby: Hit latencies defined by the controllers

2019-05-14 22:01:12 +00:00

RubyPort.cc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

RubyPort.hh

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

RubyPortProxy.cc

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

RubyPortProxy.hh

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

RubySystem.cc

mem-ruby: Remove assertion with incorrect assumption

2019-08-02 18:31:12 +00:00

RubySystem.hh

mem: Standardize mem folder header guards

2018-02-06 10:26:27 +00:00

RubySystem.py

python: Don't assume SimObjects live in the global namespace

2019-02-12 09:43:00 +00:00

SConscript

gpu-compute: AMD's baseline GPU model

2016-01-19 14:28:22 -05:00

Sequencer.cc

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

2019-05-18 10:20:20 +00:00

Sequencer.hh

ruby: Refactor some Event subclasses to lambdas

2017-07-12 20:07:05 +00:00

Sequencer.py

mem-ruby: Hit latencies defined by the controllers

2019-05-14 22:01:12 +00:00

VIPERCoalescer.cc

style: fix amd license and style issues

2018-05-16 15:32:01 +00:00

VIPERCoalescer.hh

style: fix amd license and style issues

2018-05-16 15:32:01 +00:00

VIPERCoalescer.py

python: Don't assume SimObjects live in the global namespace

2019-02-12 09:43:00 +00:00

WeightedLRUPolicy.cc

ruby: Fix initial weight in weighted LRU

2018-06-12 20:07:25 +00:00

WeightedLRUPolicy.hh

style: fix amd license and style issues

2018-05-16 15:32:01 +00:00

WeightedLRUReplacementPolicy.py

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00