4b2118ed4b
Remove this unnecessary dependency. Fixed all incorrect includes of sim/core.hh. Change-Id: I3ae282dbaeb45fbf4630237a3ab9b1a593ffbe0c Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43592 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
557 lines
20 KiB
C++
557 lines
20 KiB
C++
/*
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* Copyright (c) 2013, 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* A single PCI device configuration space entry.
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*/
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#include "dev/pci/device.hh"
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#include <list>
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/intmath.hh"
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#include "base/logging.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "debug/PciDevice.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/byteswap.hh"
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namespace gem5
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{
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PciDevice::PciDevice(const PciDeviceParams &p)
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: DmaDevice(p),
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_busAddr(p.pci_bus, p.pci_dev, p.pci_func),
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PMCAP_BASE(p.PMCAPBaseOffset),
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PMCAP_ID_OFFSET(p.PMCAPBaseOffset+PMCAP_ID),
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PMCAP_PC_OFFSET(p.PMCAPBaseOffset+PMCAP_PC),
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PMCAP_PMCS_OFFSET(p.PMCAPBaseOffset+PMCAP_PMCS),
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MSICAP_BASE(p.MSICAPBaseOffset),
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MSIXCAP_BASE(p.MSIXCAPBaseOffset),
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MSIXCAP_ID_OFFSET(p.MSIXCAPBaseOffset+MSIXCAP_ID),
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MSIXCAP_MXC_OFFSET(p.MSIXCAPBaseOffset+MSIXCAP_MXC),
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MSIXCAP_MTAB_OFFSET(p.MSIXCAPBaseOffset+MSIXCAP_MTAB),
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MSIXCAP_MPBA_OFFSET(p.MSIXCAPBaseOffset+MSIXCAP_MPBA),
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PXCAP_BASE(p.PXCAPBaseOffset),
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hostInterface(p.host->registerDevice(this, _busAddr,
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(PciIntPin)p.InterruptPin)),
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pioDelay(p.pio_latency),
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configDelay(p.config_latency)
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{
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fatal_if(p.InterruptPin >= 5,
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"Invalid PCI interrupt '%i' specified.", p.InterruptPin);
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BARs[0] = p.BAR0;
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BARs[1] = p.BAR1;
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BARs[2] = p.BAR2;
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BARs[3] = p.BAR3;
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BARs[4] = p.BAR4;
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BARs[5] = p.BAR5;
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int idx = 0;
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for (auto *bar: BARs) {
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auto *mu = dynamic_cast<PciMemUpperBar *>(bar);
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// If this is the upper 32 bits of a memory BAR, try to connect it to
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// the lower 32 bits.
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if (mu) {
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fatal_if(idx == 0,
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"First BAR in %s is upper 32 bits of a memory BAR.", idx);
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auto *ml = dynamic_cast<PciMemBar *>(BARs[idx - 1]);
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fatal_if(!ml, "Upper 32 bits of memory BAR in %s doesn't come "
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"after the lower 32.");
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mu->lower(ml);
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}
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idx++;
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}
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config.vendor = htole(p.VendorID);
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config.device = htole(p.DeviceID);
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config.command = htole(p.Command);
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config.status = htole(p.Status);
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config.revision = htole(p.Revision);
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config.progIF = htole(p.ProgIF);
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config.subClassCode = htole(p.SubClassCode);
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config.classCode = htole(p.ClassCode);
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config.cacheLineSize = htole(p.CacheLineSize);
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config.latencyTimer = htole(p.LatencyTimer);
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config.headerType = htole(p.HeaderType);
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config.bist = htole(p.BIST);
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idx = 0;
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for (auto *bar: BARs)
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config.baseAddr[idx++] = bar->write(hostInterface, 0);
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config.cardbusCIS = htole(p.CardbusCIS);
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config.subsystemVendorID = htole(p.SubsystemVendorID);
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config.subsystemID = htole(p.SubsystemID);
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config.expansionROM = htole(p.ExpansionROM);
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config.capabilityPtr = htole(p.CapabilityPtr);
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// Zero out the 7 bytes of reserved space in the PCI Config space register.
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bzero(config.reserved, 7*sizeof(uint8_t));
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config.interruptLine = htole(p.InterruptLine);
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config.interruptPin = htole(p.InterruptPin);
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config.minimumGrant = htole(p.MinimumGrant);
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config.maximumLatency = htole(p.MaximumLatency);
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// Initialize the capability lists
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// These structs are bitunions, meaning the data is stored in host
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// endianess and must be converted to Little Endian when accessed
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// by the guest
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// PMCAP
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pmcap.pid = (uint16_t)p.PMCAPCapId; // pid.cid
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pmcap.pid |= (uint16_t)p.PMCAPNextCapability << 8; //pid.next
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pmcap.pc = p.PMCAPCapabilities;
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pmcap.pmcs = p.PMCAPCtrlStatus;
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// MSICAP
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msicap.mid = (uint16_t)p.MSICAPCapId; //mid.cid
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msicap.mid |= (uint16_t)p.MSICAPNextCapability << 8; //mid.next
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msicap.mc = p.MSICAPMsgCtrl;
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msicap.ma = p.MSICAPMsgAddr;
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msicap.mua = p.MSICAPMsgUpperAddr;
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msicap.md = p.MSICAPMsgData;
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msicap.mmask = p.MSICAPMaskBits;
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msicap.mpend = p.MSICAPPendingBits;
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// MSIXCAP
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msixcap.mxid = (uint16_t)p.MSIXCAPCapId; //mxid.cid
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msixcap.mxid |= (uint16_t)p.MSIXCAPNextCapability << 8; //mxid.next
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msixcap.mxc = p.MSIXMsgCtrl;
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msixcap.mtab = p.MSIXTableOffset;
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msixcap.mpba = p.MSIXPbaOffset;
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// allocate MSIX structures if MSIXCAP_BASE
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// indicates the MSIXCAP is being used by having a
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// non-zero base address.
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// The MSIX tables are stored by the guest in
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// little endian byte-order as according the
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// PCIe specification. Make sure to take the proper
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// actions when manipulating these tables on the host
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uint16_t msixcap_mxc_ts = msixcap.mxc & 0x07ff;
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if (MSIXCAP_BASE != 0x0) {
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int msix_vecs = msixcap_mxc_ts + 1;
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MSIXTable tmp1 = {{0UL,0UL,0UL,0UL}};
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msix_table.resize(msix_vecs, tmp1);
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MSIXPbaEntry tmp2 = {0};
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int pba_size = msix_vecs / MSIXVECS_PER_PBA;
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if ((msix_vecs % MSIXVECS_PER_PBA) > 0) {
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pba_size++;
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}
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msix_pba.resize(pba_size, tmp2);
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}
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MSIX_TABLE_OFFSET = msixcap.mtab & 0xfffffffc;
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MSIX_TABLE_END = MSIX_TABLE_OFFSET +
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(msixcap_mxc_ts + 1) * sizeof(MSIXTable);
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MSIX_PBA_OFFSET = msixcap.mpba & 0xfffffffc;
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MSIX_PBA_END = MSIX_PBA_OFFSET +
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((msixcap_mxc_ts + 1) / MSIXVECS_PER_PBA)
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* sizeof(MSIXPbaEntry);
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if (((msixcap_mxc_ts + 1) % MSIXVECS_PER_PBA) > 0) {
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MSIX_PBA_END += sizeof(MSIXPbaEntry);
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}
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// PXCAP
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pxcap.pxid = (uint16_t)p.PXCAPCapId; //pxid.cid
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pxcap.pxid |= (uint16_t)p.PXCAPNextCapability << 8; //pxid.next
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pxcap.pxcap = p.PXCAPCapabilities;
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pxcap.pxdcap = p.PXCAPDevCapabilities;
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pxcap.pxdc = p.PXCAPDevCtrl;
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pxcap.pxds = p.PXCAPDevStatus;
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pxcap.pxlcap = p.PXCAPLinkCap;
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pxcap.pxlc = p.PXCAPLinkCtrl;
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pxcap.pxls = p.PXCAPLinkStatus;
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pxcap.pxdcap2 = p.PXCAPDevCap2;
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pxcap.pxdc2 = p.PXCAPDevCtrl2;
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}
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Tick
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PciDevice::readConfig(PacketPtr pkt)
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{
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int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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/* Return 0 for accesses to unimplemented PCI configspace areas */
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if (offset >= PCI_DEVICE_SPECIFIC &&
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offset < PCI_CONFIG_SIZE) {
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warn_once("Device specific PCI config space "
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"not implemented for %s!\n", this->name());
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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pkt->setLE<uint8_t>(0);
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break;
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case sizeof(uint16_t):
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pkt->setLE<uint16_t>(0);
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break;
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case sizeof(uint32_t):
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pkt->setLE<uint32_t>(0);
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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} else if (offset > PCI_CONFIG_SIZE) {
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panic("Out-of-range access to PCI config space!\n");
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}
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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pkt->setLE<uint8_t>(config.data[offset]);
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DPRINTF(PciDevice,
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"readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
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_busAddr.dev, _busAddr.func, offset,
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(uint32_t)pkt->getLE<uint8_t>());
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break;
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case sizeof(uint16_t):
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pkt->setLE<uint16_t>(*(uint16_t*)&config.data[offset]);
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DPRINTF(PciDevice,
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"readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
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_busAddr.dev, _busAddr.func, offset,
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(uint32_t)pkt->getLE<uint16_t>());
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break;
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case sizeof(uint32_t):
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pkt->setLE<uint32_t>(*(uint32_t*)&config.data[offset]);
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DPRINTF(PciDevice,
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"readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
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_busAddr.dev, _busAddr.func, offset,
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(uint32_t)pkt->getLE<uint32_t>());
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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pkt->makeAtomicResponse();
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return configDelay;
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}
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AddrRangeList
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PciDevice::getAddrRanges() const
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{
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AddrRangeList ranges;
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PciCommandRegister command = letoh(config.command);
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for (auto *bar: BARs) {
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if (command.ioSpace && bar->isIo())
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ranges.push_back(bar->range());
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if (command.memorySpace && bar->isMem())
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ranges.push_back(bar->range());
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}
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return ranges;
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}
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Tick
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PciDevice::writeConfig(PacketPtr pkt)
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{
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int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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/* No effect if we write to config space that is not implemented*/
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if (offset >= PCI_DEVICE_SPECIFIC &&
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offset < PCI_CONFIG_SIZE) {
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warn_once("Device specific PCI config space "
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"not implemented for %s!\n", this->name());
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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case sizeof(uint16_t):
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case sizeof(uint32_t):
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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} else if (offset > PCI_CONFIG_SIZE) {
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panic("Out-of-range access to PCI config space!\n");
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}
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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switch (offset) {
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case PCI0_INTERRUPT_LINE:
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config.interruptLine = pkt->getLE<uint8_t>();
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break;
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case PCI_CACHE_LINE_SIZE:
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config.cacheLineSize = pkt->getLE<uint8_t>();
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break;
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case PCI_LATENCY_TIMER:
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config.latencyTimer = pkt->getLE<uint8_t>();
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break;
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/* Do nothing for these read-only registers */
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case PCI0_INTERRUPT_PIN:
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case PCI0_MINIMUM_GRANT:
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case PCI0_MAXIMUM_LATENCY:
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case PCI_CLASS_CODE:
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case PCI_REVISION_ID:
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break;
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default:
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panic("writing to a read only register");
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}
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DPRINTF(PciDevice,
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"writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
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_busAddr.dev, _busAddr.func, offset,
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(uint32_t)pkt->getLE<uint8_t>());
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break;
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case sizeof(uint16_t):
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switch (offset) {
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case PCI_COMMAND:
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config.command = pkt->getLE<uint8_t>();
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// IO or memory space may have been enabled/disabled.
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pioPort.sendRangeChange();
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break;
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case PCI_STATUS:
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config.status = pkt->getLE<uint8_t>();
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break;
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case PCI_CACHE_LINE_SIZE:
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config.cacheLineSize = pkt->getLE<uint8_t>();
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break;
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default:
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panic("writing to a read only register");
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}
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DPRINTF(PciDevice,
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"writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
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_busAddr.dev, _busAddr.func, offset,
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(uint32_t)pkt->getLE<uint16_t>());
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break;
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case sizeof(uint32_t):
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switch (offset) {
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case PCI0_BASE_ADDR0:
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case PCI0_BASE_ADDR1:
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case PCI0_BASE_ADDR2:
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case PCI0_BASE_ADDR3:
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case PCI0_BASE_ADDR4:
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case PCI0_BASE_ADDR5:
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{
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int num = BAR_NUMBER(offset);
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auto *bar = BARs[num];
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config.baseAddr[num] =
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htole(bar->write(hostInterface, pkt->getLE<uint32_t>()));
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pioPort.sendRangeChange();
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}
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break;
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case PCI0_ROM_BASE_ADDR:
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if (letoh(pkt->getLE<uint32_t>()) == 0xfffffffe)
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config.expansionROM = htole((uint32_t)0xffffffff);
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else
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config.expansionROM = pkt->getLE<uint32_t>();
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break;
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case PCI_COMMAND:
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// This could also clear some of the error bits in the Status
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// register. However they should never get set, so lets ignore
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// it for now
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config.command = pkt->getLE<uint32_t>();
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// IO or memory space may have been enabled/disabled.
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pioPort.sendRangeChange();
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break;
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default:
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DPRINTF(PciDevice, "Writing to a read only register");
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}
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DPRINTF(PciDevice,
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"writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
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_busAddr.dev, _busAddr.func, offset,
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(uint32_t)pkt->getLE<uint32_t>());
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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pkt->makeAtomicResponse();
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return configDelay;
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}
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void
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PciDevice::serialize(CheckpointOut &cp) const
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{
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SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
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// serialize the capability list registers
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paramOut(cp, csprintf("pmcap.pid"), uint16_t(pmcap.pid));
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paramOut(cp, csprintf("pmcap.pc"), uint16_t(pmcap.pc));
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paramOut(cp, csprintf("pmcap.pmcs"), uint16_t(pmcap.pmcs));
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paramOut(cp, csprintf("msicap.mid"), uint16_t(msicap.mid));
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paramOut(cp, csprintf("msicap.mc"), uint16_t(msicap.mc));
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paramOut(cp, csprintf("msicap.ma"), uint32_t(msicap.ma));
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SERIALIZE_SCALAR(msicap.mua);
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paramOut(cp, csprintf("msicap.md"), uint16_t(msicap.md));
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SERIALIZE_SCALAR(msicap.mmask);
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SERIALIZE_SCALAR(msicap.mpend);
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paramOut(cp, csprintf("msixcap.mxid"), uint16_t(msixcap.mxid));
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paramOut(cp, csprintf("msixcap.mxc"), uint16_t(msixcap.mxc));
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paramOut(cp, csprintf("msixcap.mtab"), uint32_t(msixcap.mtab));
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paramOut(cp, csprintf("msixcap.mpba"), uint32_t(msixcap.mpba));
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// Only serialize if we have a non-zero base address
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if (MSIXCAP_BASE != 0x0) {
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uint16_t msixcap_mxc_ts = msixcap.mxc & 0x07ff;
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int msix_array_size = msixcap_mxc_ts + 1;
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int pba_array_size = msix_array_size/MSIXVECS_PER_PBA;
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if ((msix_array_size % MSIXVECS_PER_PBA) > 0) {
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pba_array_size++;
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}
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SERIALIZE_SCALAR(msix_array_size);
|
|
SERIALIZE_SCALAR(pba_array_size);
|
|
|
|
for (int i = 0; i < msix_array_size; i++) {
|
|
paramOut(cp, csprintf("msix_table[%d].addr_lo", i),
|
|
msix_table[i].fields.addr_lo);
|
|
paramOut(cp, csprintf("msix_table[%d].addr_hi", i),
|
|
msix_table[i].fields.addr_hi);
|
|
paramOut(cp, csprintf("msix_table[%d].msg_data", i),
|
|
msix_table[i].fields.msg_data);
|
|
paramOut(cp, csprintf("msix_table[%d].vec_ctrl", i),
|
|
msix_table[i].fields.vec_ctrl);
|
|
}
|
|
for (int i = 0; i < pba_array_size; i++) {
|
|
paramOut(cp, csprintf("msix_pba[%d].bits", i),
|
|
msix_pba[i].bits);
|
|
}
|
|
}
|
|
|
|
paramOut(cp, csprintf("pxcap.pxid"), uint16_t(pxcap.pxid));
|
|
paramOut(cp, csprintf("pxcap.pxcap"), uint16_t(pxcap.pxcap));
|
|
paramOut(cp, csprintf("pxcap.pxdcap"), uint32_t(pxcap.pxdcap));
|
|
paramOut(cp, csprintf("pxcap.pxdc"), uint16_t(pxcap.pxdc));
|
|
paramOut(cp, csprintf("pxcap.pxds"), uint16_t(pxcap.pxds));
|
|
paramOut(cp, csprintf("pxcap.pxlcap"), uint32_t(pxcap.pxlcap));
|
|
paramOut(cp, csprintf("pxcap.pxlc"), uint16_t(pxcap.pxlc));
|
|
paramOut(cp, csprintf("pxcap.pxls"), uint16_t(pxcap.pxls));
|
|
paramOut(cp, csprintf("pxcap.pxdcap2"), uint32_t(pxcap.pxdcap2));
|
|
paramOut(cp, csprintf("pxcap.pxdc2"), uint32_t(pxcap.pxdc2));
|
|
}
|
|
|
|
void
|
|
PciDevice::unserialize(CheckpointIn &cp)
|
|
{
|
|
UNSERIALIZE_ARRAY(config.data,
|
|
sizeof(config.data) / sizeof(config.data[0]));
|
|
|
|
for (int idx = 0; idx < BARs.size(); idx++)
|
|
BARs[idx]->write(hostInterface, config.baseAddr[idx]);
|
|
|
|
// unserialize the capability list registers
|
|
uint16_t tmp16;
|
|
uint32_t tmp32;
|
|
paramIn(cp, csprintf("pmcap.pid"), tmp16);
|
|
pmcap.pid = tmp16;
|
|
paramIn(cp, csprintf("pmcap.pc"), tmp16);
|
|
pmcap.pc = tmp16;
|
|
paramIn(cp, csprintf("pmcap.pmcs"), tmp16);
|
|
pmcap.pmcs = tmp16;
|
|
|
|
paramIn(cp, csprintf("msicap.mid"), tmp16);
|
|
msicap.mid = tmp16;
|
|
paramIn(cp, csprintf("msicap.mc"), tmp16);
|
|
msicap.mc = tmp16;
|
|
paramIn(cp, csprintf("msicap.ma"), tmp32);
|
|
msicap.ma = tmp32;
|
|
UNSERIALIZE_SCALAR(msicap.mua);
|
|
paramIn(cp, csprintf("msicap.md"), tmp16);;
|
|
msicap.md = tmp16;
|
|
UNSERIALIZE_SCALAR(msicap.mmask);
|
|
UNSERIALIZE_SCALAR(msicap.mpend);
|
|
|
|
paramIn(cp, csprintf("msixcap.mxid"), tmp16);
|
|
msixcap.mxid = tmp16;
|
|
paramIn(cp, csprintf("msixcap.mxc"), tmp16);
|
|
msixcap.mxc = tmp16;
|
|
paramIn(cp, csprintf("msixcap.mtab"), tmp32);
|
|
msixcap.mtab = tmp32;
|
|
paramIn(cp, csprintf("msixcap.mpba"), tmp32);
|
|
msixcap.mpba = tmp32;
|
|
|
|
// Only allocate if MSIXCAP_BASE is not 0x0
|
|
if (MSIXCAP_BASE != 0x0) {
|
|
int msix_array_size;
|
|
int pba_array_size;
|
|
|
|
UNSERIALIZE_SCALAR(msix_array_size);
|
|
UNSERIALIZE_SCALAR(pba_array_size);
|
|
|
|
MSIXTable tmp1 = {{0UL, 0UL, 0UL, 0UL}};
|
|
msix_table.resize(msix_array_size, tmp1);
|
|
|
|
MSIXPbaEntry tmp2 = {0};
|
|
msix_pba.resize(pba_array_size, tmp2);
|
|
|
|
for (int i = 0; i < msix_array_size; i++) {
|
|
paramIn(cp, csprintf("msix_table[%d].addr_lo", i),
|
|
msix_table[i].fields.addr_lo);
|
|
paramIn(cp, csprintf("msix_table[%d].addr_hi", i),
|
|
msix_table[i].fields.addr_hi);
|
|
paramIn(cp, csprintf("msix_table[%d].msg_data", i),
|
|
msix_table[i].fields.msg_data);
|
|
paramIn(cp, csprintf("msix_table[%d].vec_ctrl", i),
|
|
msix_table[i].fields.vec_ctrl);
|
|
}
|
|
for (int i = 0; i < pba_array_size; i++) {
|
|
paramIn(cp, csprintf("msix_pba[%d].bits", i),
|
|
msix_pba[i].bits);
|
|
}
|
|
}
|
|
|
|
paramIn(cp, csprintf("pxcap.pxid"), tmp16);
|
|
pxcap.pxid = tmp16;
|
|
paramIn(cp, csprintf("pxcap.pxcap"), tmp16);
|
|
pxcap.pxcap = tmp16;
|
|
paramIn(cp, csprintf("pxcap.pxdcap"), tmp32);
|
|
pxcap.pxdcap = tmp32;
|
|
paramIn(cp, csprintf("pxcap.pxdc"), tmp16);
|
|
pxcap.pxdc = tmp16;
|
|
paramIn(cp, csprintf("pxcap.pxds"), tmp16);
|
|
pxcap.pxds = tmp16;
|
|
paramIn(cp, csprintf("pxcap.pxlcap"), tmp32);
|
|
pxcap.pxlcap = tmp32;
|
|
paramIn(cp, csprintf("pxcap.pxlc"), tmp16);
|
|
pxcap.pxlc = tmp16;
|
|
paramIn(cp, csprintf("pxcap.pxls"), tmp16);
|
|
pxcap.pxls = tmp16;
|
|
paramIn(cp, csprintf("pxcap.pxdcap2"), tmp32);
|
|
pxcap.pxdcap2 = tmp32;
|
|
paramIn(cp, csprintf("pxcap.pxdc2"), tmp32);
|
|
pxcap.pxdc2 = tmp32;
|
|
pioPort.sendRangeChange();
|
|
}
|
|
|
|
} // namespace gem5
|