4060208a04
Per the AMD64 Architecture Programming Manual: The size of the count register (CX, ECX, or RCX) depends on the address-size attribute of the JrCXZ instruction. Therefore, JRCXZ can only be executed in 64-bit mode and In 64-bit mode, the operand size defaults to 64 bits. The processor sign-extends the 8-bit displacement value to 64 bits before adding it to the RIP. This patch also renames the instruction from JRCX to JRCXZ to match the language in the programming manual. Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40195 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>