343ef29173
Change-Id: I30b4736ebe44b8429a32c8951af6e654a1238ae6 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49346 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
104 lines
3.9 KiB
Python
104 lines
3.9 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from typing import Optional
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from components_library.runtime import get_runtime_isa
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from components_library.processors.abstract_core import AbstractCore
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from .cpu_types import CPUTypes
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from ..isas import ISA
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from ..utils.override import overrides
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from m5.objects import (
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BaseMMU,
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Port,
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AtomicSimpleCPU,
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DerivO3CPU,
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TimingSimpleCPU,
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BaseCPU,
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Process,
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)
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class SimpleCore(AbstractCore):
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def __init__(self, cpu_type: CPUTypes, core_id: int):
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super(SimpleCore, self).__init__(cpu_type=cpu_type)
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if cpu_type == CPUTypes.ATOMIC:
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self.core = AtomicSimpleCPU(cpu_id=core_id)
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elif cpu_type == CPUTypes.O3:
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self.core = DerivO3CPU(cpu_id=core_id)
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elif cpu_type == CPUTypes.TIMING:
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self.core = TimingSimpleCPU(cpu_id=core_id)
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elif cpu_type == CPUTypes.KVM:
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self.core = X86KvmCPU(cpu_id=core_id)
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else:
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raise NotImplementedError
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self.core.createThreads()
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def get_simobject(self) -> BaseCPU:
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return self.core
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@overrides(AbstractCore)
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def connect_icache(self, port: Port) -> None:
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self.core.icache_port = port
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@overrides(AbstractCore)
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def connect_dcache(self, port: Port) -> None:
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self.core.dcache_port = port
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@overrides(AbstractCore)
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def connect_walker_ports(self, port1: Port, port2: Port) -> None:
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self.core.mmu.connectWalkerPorts(port1, port2)
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@overrides(AbstractCore)
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def set_workload(self, process: Process) -> None:
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self.core.workload = process
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@overrides(AbstractCore)
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def set_switched_out(self, value: bool) -> None:
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self.core.switched_out = value
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@overrides(AbstractCore)
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def connect_interrupt(
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self, interrupt_requestor: Optional[Port] = None,
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interrupt_responce: Optional[Port] = None
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) -> None:
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# TODO: This model assumes that we will only create an interrupt
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# controller as we require it. Not sure how true this is in all cases.
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self.core.createInterruptController()
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if get_runtime_isa() == ISA.X86:
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self.core.interrupts[0].pio = interrupt_requestor
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self.core.interrupts[0].int_requestor = interrupt_responce
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self.core.interrupts[0].int_responder = interrupt_requestor
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@overrides(AbstractCore)
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def get_mmu(self) -> BaseMMU:
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return self.core.mmu
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