343ef29173
Change-Id: I30b4736ebe44b8429a32c8951af6e654a1238ae6 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49346 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
102 lines
3.8 KiB
Python
102 lines
3.8 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from abc import ABCMeta, abstractmethod
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from typing import Optional
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from .cpu_types import CPUTypes
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from m5.objects import BaseMMU, Port, SubSystem
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class AbstractCore(SubSystem):
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__metaclass__ = ABCMeta
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def __init__(self, cpu_type: CPUTypes):
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super(AbstractCore, self).__init__()
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self._cpu_type = cpu_type
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def get_type(self) -> CPUTypes:
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return self._cpu_type
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@abstractmethod
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def connect_icache(self, port: Port) -> None:
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"""
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This function should connect the response port from the instruction
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cache to the right request port on the core.
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:param port: The response port from the icache to connect to.
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"""
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raise NotImplementedError
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@abstractmethod
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def connect_dcache(self, port: Port) -> None:
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"""
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This function should connect the response port from the data cache to
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the right request port on the core.
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:param port: The response port from the icache to connect to.
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"""
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raise NotImplementedError
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@abstractmethod
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def connect_walker_ports(self, port1: Port, port2: Port) -> None:
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"""
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Connect the response port from itb and dtb to their respective request
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ports in the core.
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:param port1: The response port from itb walker to connect to.
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:param port2: The response port from dtb walker to connect to.
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"""
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raise NotImplementedError
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@abstractmethod
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def set_workload(self, process: "Process") -> None:
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raise NotImplementedError
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@abstractmethod
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def set_switched_out(self, value: bool) -> None:
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raise NotImplementedError
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@abstractmethod
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def connect_interrupt(
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self, interrupt_requestor: Optional[Port] = None,
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interrupt_responce: Optional[Port] = None
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) -> None:
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""" Connect the core interrupts to the interrupt controller
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This function is usually called from the cache hierarchy since the
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optional ports can be implemented as cache ports.
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"""
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raise NotImplementedError
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@abstractmethod
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def get_mmu(self) -> BaseMMU:
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""" Return the MMU for this core.
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This is used in the board to setup system-specific MMU settings.
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"""
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raise NotImplementedError
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