3783cc0de0
The runtime coherence check should check the cache heirarchy, not the global protocol so it can differentiate between Ruby and classic. This patch also removes some unnecessary includes and fails earlier in MESI_Two_Level if that protocol isn't built. Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49345 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
207 lines
7.7 KiB
Python
207 lines
7.7 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from .abstract_ruby_cache_hierarhcy import AbstractRubyCacheHierarchy
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from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy
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from ...coherence_protocol import CoherenceProtocol
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from ...isas import ISA
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from ...boards.abstract_board import AbstractBoard
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from ...runtime import get_runtime_coherence_protocol, get_runtime_isa
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from .topologies.simple_pt2pt import SimplePt2Pt
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from .caches.mesi_two_level.l1_cache import L1Cache
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from .caches.mesi_two_level.l2_cache import L2Cache
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from .caches.mesi_two_level.directory import Directory
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from .caches.mesi_two_level.dma_controller import DMAController
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from m5.objects import (
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RubySystem,
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RubySequencer,
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DMASequencer,
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RubyPortProxy,
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)
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class MESITwoLevelCacheHierarchy(
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AbstractRubyCacheHierarchy, AbstractTwoLevelCacheHierarchy
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):
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"""A two level private L1 shared L2 MESI hierarchy.
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In addition to the normal two level parameters, you can also change the
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number of L2 banks in this protocol.
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The on-chip network is a point-to-point all-to-all simple network.
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"""
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def __init__(
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self,
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l1i_size: str,
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l1i_assoc: str,
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l1d_size: str,
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l1d_assoc: str,
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l2_size: str,
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l2_assoc: str,
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num_l2_banks: int,
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):
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if (
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get_runtime_coherence_protocol()
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!= CoherenceProtocol.MESI_TWO_LEVEL
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):
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raise EnvironmentError(
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"The MESITwoLevelCacheHierarchy must be used with with the "
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"MESI_Two_Level coherence protocol."
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)
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AbstractRubyCacheHierarchy.__init__(self=self)
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AbstractTwoLevelCacheHierarchy.__init__(
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self,
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l1i_size=l1i_size,
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l1i_assoc=l1i_assoc,
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l1d_size=l1d_size,
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l1d_assoc=l1d_assoc,
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l2_size=l2_size,
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l2_assoc=l2_assoc,
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)
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self._num_l2_banks = num_l2_banks
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def incorporate_cache(self, board: AbstractBoard) -> None:
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cache_line_size = board.get_cache_line_size()
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self.ruby_system = RubySystem()
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# MESI_Two_Level needs 5 virtual networks
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self.ruby_system.number_of_virtual_networks = 5
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self.ruby_system.network = SimplePt2Pt(self.ruby_system)
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self.ruby_system.network.number_of_virtual_networks = 5
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self._l1_controllers = []
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for i, core in enumerate(board.get_processor().get_cores()):
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cache = L1Cache(
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self._l1i_size,
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self._l1i_assoc,
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self._l1d_size,
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self._l1d_assoc,
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self.ruby_system.network,
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core,
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self._num_l2_banks,
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cache_line_size,
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get_runtime_isa(),
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board.get_clock_domain(),
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)
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if board.has_io_bus():
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cache.sequencer = RubySequencer(
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version=i,
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dcache=cache.L1Dcache,
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clk_domain=cache.clk_domain,
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pio_request_port=board.get_io_bus().cpu_side_ports,
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mem_request_port=board.get_io_bus().cpu_side_ports,
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pio_response_port=board.get_io_bus().mem_side_ports,
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)
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else:
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cache.sequencer = RubySequencer(
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version=i,
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dcache=cache.L1Dcache,
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clk_domain=cache.clk_domain,
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)
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cache.ruby_system = self.ruby_system
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core.connect_icache(cache.sequencer.in_ports)
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core.connect_dcache(cache.sequencer.in_ports)
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core.connect_walker_ports(
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cache.sequencer.in_ports, cache.sequencer.in_ports
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)
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# Connect the interrupt ports
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if get_runtime_isa() == ISA.X86:
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int_req_port = cache.sequencer.interrupt_out_port
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int_resp_port = cache.sequencer.in_ports
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core.connect_interrupt(int_req_port, int_resp_port)
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self._l1_controllers.append(cache)
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self._l2_controllers = [
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L2Cache(
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self._l2_size,
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self._l2_assoc,
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self.ruby_system.network,
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self._num_l2_banks,
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cache_line_size,
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)
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for _ in range(self._num_l2_banks)
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]
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# TODO: Make this prettier: The problem is not being able to proxy
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# the ruby system correctly
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for cache in self._l2_controllers:
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cache.ruby_system = self.ruby_system
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self._directory_controllers = [
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Directory(self.ruby_system.network, cache_line_size, range, port)
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for range, port in board.get_memory().get_mem_ports()
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]
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# TODO: Make this prettier: The problem is not being able to proxy
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# the ruby system correctly
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for dir in self._directory_controllers:
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dir.ruby_system = self.ruby_system
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dma_ports = board.get_dma_ports()
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self._dma_controllers = []
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for i, port in enumerate(dma_ports):
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ctrl = DMAController(self.ruby_system.network, cache_line_size)
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ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
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self._dma_controllers.append(ctrl)
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ctrl.ruby_system = self.ruby_system
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self.ruby_system.num_of_sequencers = len(self._l1_controllers) + len(
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self._dma_controllers
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)
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self.ruby_system.l1_controllers = self._l1_controllers
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self.ruby_system.l2_controllers = self._l2_controllers
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self.ruby_system.directory_controllers = self._directory_controllers
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if len(self._dma_controllers) != 0:
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self.ruby_system.dma_controllers = self._dma_controllers
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# Create the network and connect the controllers.
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self.ruby_system.network.connectControllers(
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self._l1_controllers
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+ self._l2_controllers
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+ self._directory_controllers
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+ self._dma_controllers
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)
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self.ruby_system.network.setup_buffers()
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# Set up a proxy port for the system_port. Used for load binaries and
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# other functional-only things.
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self.ruby_system.sys_port_proxy = RubyPortProxy()
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board.connect_system_port(self.ruby_system.sys_port_proxy.in_ports)
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