9ce797e130
This change adds a check for coherent I/O ports from the board. This change allows us to move some of the cache hierarchy specific code out of the board and into the cache hierarchies. Change-Id: Ib8144b6d8579ee71e86e4823d2cd396f9cb254ba Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49363 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
133 lines
5.1 KiB
Python
133 lines
5.1 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from components_library.cachehierarchies.classic.\
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abstract_classic_cache_hierarchy import (
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AbstractClassicCacheHierarchy,
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)
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from ..abstract_cache_hierarchy import AbstractCacheHierarchy
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from ...boards.abstract_board import AbstractBoard
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from ...isas import ISA
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from ...runtime import get_runtime_isa
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from m5.objects import Bridge, BaseXBar, SystemXBar, BadAddr, Port
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from typing import Optional
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from ...utils.override import *
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class NoCache(AbstractClassicCacheHierarchy):
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"""
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No cache hierarchy. The CPUs are connected straight to the memory bus.
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By default a SystemXBar of width 64bit is used, though this can be
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configured via the constructor.
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NOTE: At present this does not work with FS. The following error is
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received:
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```
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...
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build/X86/mem/snoop_filter.cc:277: panic: panic condition
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(sf_item.requested & req_mask).none() occurred: SF value
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0000000000000000000000000000000000000000000000000000000000000000 ...
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missing the original request
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Memory Usage: 3554472 KBytes
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Program aborted at tick 1668400099164
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--- BEGIN LIBC BACKTRACE ---
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...
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```
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"""
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@staticmethod
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def _get_default_membus() -> SystemXBar:
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"""
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A method used to obtain the default memory bus of 64 bit in width for
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the NoCache CacheHierarchy.
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:returns: The default memory bus for the NoCache CacheHierarchy.
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:rtype: SystemXBar
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"""
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membus = SystemXBar(width=64)
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membus.badaddr_responder = BadAddr()
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membus.default = membus.badaddr_responder.pio
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return membus
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def __init__(
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self, membus: Optional[BaseXBar] = _get_default_membus.__func__()
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) -> None:
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"""
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:param membus: The memory bus for this setup. This parameter is
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optional and will default toa 64 bit width SystemXBar is not specified.
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:type membus: Optional[BaseXBar]
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"""
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super(NoCache, self).__init__()
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self.membus = membus
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@overrides(AbstractClassicCacheHierarchy)
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def get_mem_side_port(self) -> Port:
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return self.membus.mem_side_ports
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@overrides(AbstractClassicCacheHierarchy)
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def get_cpu_side_port(self) -> Port:
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return self.membus.cpu_side_ports
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@overrides(AbstractCacheHierarchy)
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def incorporate_cache(self, board: AbstractBoard) -> None:
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if board.has_coherent_io():
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self._setup_coherent_io_bridge(board)
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for core in board.get_processor().get_cores():
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core.connect_icache(self.membus.cpu_side_ports)
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core.connect_dcache(self.membus.cpu_side_ports)
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core.connect_walker_ports(
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self.membus.cpu_side_ports, self.membus.cpu_side_ports
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)
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if get_runtime_isa() == ISA.X86:
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int_req_port = self.membus.mem_side_ports
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int_resp_port = self.membus.cpu_side_ports
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core.connect_interrupt(int_req_port, int_resp_port)
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else:
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core.connect_interrupt()
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# Set up the system port for functional access from the simulator.
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board.connect_system_port(self.membus.cpu_side_ports)
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for cntr in board.get_memory().get_memory_controllers():
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cntr.port = self.membus.mem_side_ports
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def _setup_coherent_io_bridge(self, board: AbstractBoard) -> None:
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"""Create a bridge from I/O back to membus"""
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self.iobridge = Bridge(delay="10ns", ranges=board.mem_ranges)
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self.iobridge.mem_side_port = self.membus.cpu_side_ports
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self.iobridge.cpu_side_port = board.get_mem_side_coherent_io_port()
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