569e21f798
`get_runtime_isa()` has been deprecated for some time. It is a leftover piece of code from when gem5 was compiled to a single ISA and that ISA used to configure the simulated system to use that ISA. Since multi-ISA compilations are possible, `get_runtime_isa()` should not be used. Unless the gem5 binary is compiled to a single ISA, a failure will occur. The new proceedure for specify which ISA to use is by the setting of the correct `BaseCPU` implementation. E.g., `X86SimpleTimingCPU` of `ArmO3CPU`. This patch removes the remaining `get_runtime_isa()` instances and removes the function itself. The `SimpleCore` class has been updated to allow for it's CPU factory to return a class, needed by scripts in "configs/common". The deprecated functionality in the standard library, which allowed for the specifying of an ISA when setting up a processor and/or core has also been removed. Setting an ISA is now manditory. Fixes #216.
339 lines
11 KiB
Python
339 lines
11 KiB
Python
# Copyright (c) 2012, 2017-2018, 2021 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import math
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import (
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addToPath,
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fatal,
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)
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from gem5.isas import ISA
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addToPath("../")
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from common import (
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FileSystemConfig,
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MemConfig,
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ObjectList,
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)
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from network import Network
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from topologies import *
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def define_options(parser):
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# By default, ruby uses the simple timing cpu and the X86 ISA
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parser.set_defaults(cpu_type="X86TimingSimpleCPU")
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parser.add_argument(
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"--ruby-clock",
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action="store",
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type=str,
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default="2GHz",
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help="Clock for blocks running at Ruby system's speed",
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)
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parser.add_argument(
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"--access-backing-store",
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action="store_true",
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default=False,
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help="Should ruby maintain a second copy of memory",
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)
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# Options related to cache structure
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parser.add_argument(
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"--ports",
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action="store",
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type=int,
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default=4,
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help="used of transitions per cycle which is a proxy \
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for the number of ports.",
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)
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# network options are in network/Network.py
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# ruby mapping options
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parser.add_argument(
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"--numa-high-bit",
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type=int,
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default=0,
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help="high order address bit to use for numa mapping. "
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"0 = highest bit, not specified = lowest bit",
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)
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parser.add_argument(
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"--interleaving-bits",
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type=int,
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default=0,
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help="number of bits to specify interleaving "
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"in directory, memory controllers and caches. "
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"0 = not specified",
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)
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parser.add_argument(
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"--xor-low-bit",
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type=int,
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default=20,
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help="hashing bit for channel selection"
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"see MemConfig for explanation of the default"
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"parameter. If set to 0, xor_high_bit is also"
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"set to 0.",
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)
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parser.add_argument(
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"--recycle-latency",
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type=int,
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default=10,
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help="Recycle latency for ruby controller input buffers",
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)
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protocol = buildEnv["PROTOCOL"]
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exec(f"from . import {protocol}")
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eval(f"{protocol}.define_options(parser)")
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Network.define_options(parser)
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def setup_memory_controllers(system, ruby, dir_cntrls, options):
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if options.numa_high_bit:
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block_size_bits = (
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options.numa_high_bit + 1 - int(math.log(options.num_dirs, 2))
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)
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ruby.block_size_bytes = 2 ** (block_size_bits)
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else:
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ruby.block_size_bytes = options.cacheline_size
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ruby.memory_size_bits = 48
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index = 0
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mem_ctrls = []
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crossbars = []
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if options.numa_high_bit:
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dir_bits = int(math.log(options.num_dirs, 2))
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intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1)
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else:
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# if the numa_bit is not specified, set the directory bits as the
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# lowest bits above the block offset bits
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intlv_size = options.cacheline_size
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# Sets bits to be used for interleaving. Creates memory controllers
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# attached to a directory controller. A separate controller is created
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# for each address range as the abstract memory can handle only one
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# contiguous address range as of now.
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for dir_cntrl in dir_cntrls:
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crossbar = None
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if len(system.mem_ranges) > 1:
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crossbar = IOXBar()
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crossbars.append(crossbar)
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dir_cntrl.memory_out_port = crossbar.cpu_side_ports
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dir_ranges = []
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for r in system.mem_ranges:
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mem_type = ObjectList.mem_list.get(options.mem_type)
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dram_intf = MemConfig.create_mem_intf(
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mem_type,
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r,
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index,
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int(math.log(options.num_dirs, 2)),
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intlv_size,
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options.xor_low_bit,
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)
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if issubclass(mem_type, DRAMInterface):
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mem_ctrl = m5.objects.MemCtrl(dram=dram_intf)
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else:
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mem_ctrl = dram_intf
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if options.access_backing_store:
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dram_intf.kvm_map = False
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mem_ctrls.append(mem_ctrl)
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dir_ranges.append(dram_intf.range)
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if crossbar != None:
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mem_ctrl.port = crossbar.mem_side_ports
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else:
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mem_ctrl.port = dir_cntrl.memory_out_port
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# Enable low-power DRAM states if option is set
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if issubclass(mem_type, DRAMInterface):
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mem_ctrl.dram.enable_dram_powerdown = (
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options.enable_dram_powerdown
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)
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index += 1
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dir_cntrl.addr_ranges = dir_ranges
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system.mem_ctrls = mem_ctrls
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if len(crossbars) > 0:
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ruby.crossbars = crossbars
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def create_topology(controllers, options):
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"""Called from create_system in configs/ruby/<protocol>.py
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Must return an object which is a subclass of BaseTopology
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found in configs/topologies/BaseTopology.py
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This is a wrapper for the legacy topologies.
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"""
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exec(f"import topologies.{options.topology} as Topo")
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topology = eval(f"Topo.{options.topology}(controllers)")
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return topology
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def create_system(
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options,
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full_system,
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system,
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piobus=None,
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dma_ports=[],
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bootmem=None,
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cpus=None,
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):
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system.ruby = RubySystem()
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ruby = system.ruby
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# Generate pseudo filesystem
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FileSystemConfig.config_filesystem(system, options)
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# Create the network object
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(
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network,
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IntLinkClass,
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ExtLinkClass,
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RouterClass,
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InterfaceClass,
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) = Network.create_network(options, ruby)
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ruby.network = network
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if cpus is None:
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cpus = system.cpu
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protocol = buildEnv["PROTOCOL"]
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exec(f"from . import {protocol}")
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try:
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(cpu_sequencers, dir_cntrls, topology) = eval(
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"%s.create_system(options, full_system, system, dma_ports,\
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bootmem, ruby, cpus)"
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% protocol
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)
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except:
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print(f"Error: could not create sytem for ruby protocol {protocol}")
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raise
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# Create the network topology
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topology.makeTopology(
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options, network, IntLinkClass, ExtLinkClass, RouterClass
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)
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# Register the topology elements with faux filesystem (SE mode only)
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if not full_system:
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topology.registerTopology(options)
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# Initialize network based on topology
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Network.init_network(options, network, InterfaceClass)
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# Create a port proxy for connecting the system port. This is
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# independent of the protocol and kept in the protocol-agnostic
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# part (i.e. here).
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sys_port_proxy = RubyPortProxy(ruby_system=ruby)
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if piobus is not None:
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sys_port_proxy.pio_request_port = piobus.cpu_side_ports
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# Give the system port proxy a SimObject parent without creating a
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# full-fledged controller
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system.sys_port_proxy = sys_port_proxy
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# Connect the system port for loading of binaries etc
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system.system_port = system.sys_port_proxy.in_ports
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setup_memory_controllers(system, ruby, dir_cntrls, options)
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# Connect the cpu sequencers and the piobus
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if piobus != None:
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for cpu_seq in cpu_sequencers:
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cpu_seq.connectIOPorts(piobus)
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ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
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ruby._cpu_ports = cpu_sequencers
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ruby.num_of_sequencers = len(cpu_sequencers)
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# Create a backing copy of physical memory in case required
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if options.access_backing_store:
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ruby.access_backing_store = True
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ruby.phys_mem = SimpleMemory(
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range=system.mem_ranges[0], in_addr_map=False
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)
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def create_directories(options, bootmem, ruby_system, system):
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dir_cntrl_nodes = []
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for i in range(options.num_dirs):
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dir_cntrl = Directory_Controller()
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dir_cntrl.version = i
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dir_cntrl.directory = RubyDirectoryMemory()
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dir_cntrl.ruby_system = ruby_system
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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if bootmem is not None:
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rom_dir_cntrl = Directory_Controller()
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rom_dir_cntrl.directory = RubyDirectoryMemory()
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rom_dir_cntrl.ruby_system = ruby_system
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rom_dir_cntrl.version = i + 1
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rom_dir_cntrl.memory = bootmem.port
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rom_dir_cntrl.addr_ranges = bootmem.range
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return (dir_cntrl_nodes, rom_dir_cntrl)
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return (dir_cntrl_nodes, None)
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def send_evicts(options):
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# currently, 2 scenarios warrant forwarding evictions to the CPU:
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# 1. The O3 model must keep the LSQ coherent with the caches
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# 2. The x86 mwait instruction is built on top of coherence invalidations
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# 3. The local exclusive monitor in ARM systems
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if isinstance(
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options.cpu_type, DerivO3CPU
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) or ObjectList.CPUList().get_isa(options.cpu_type) in [ISA.X86, ISA.ARM]:
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return True
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return False
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