Files
gem5/src
Robert Hauser 3d2d960f10 arch-riscv: fix return value of pseudo instruction
Only the lower 32 bit of return values of pseudo instructions are
stored (in a0). Therefore, the upper 32 bit are stored in a1 to
enable a correct return value.

Change-Id: Idf33c325033281fc191a9285eb5d34fd4965cde9
2024-03-11 15:32:15 +00:00
..
2024-01-23 11:35:54 -08:00