gem5/src/cpu at 3a5a20769b2ba15905fc2e0a833a8ecbf3098646 - gem5

checker

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

memtest

Fix some of the memory leaks related to writebacks

2007-03-12 13:15:32 -05:00

o3

fix segfault when peer owner attempts to use functional port

2007-03-13 17:34:52 -04:00

ozone

fix segfault when peer owner attempts to use functional port

2007-03-13 17:34:52 -04:00

simple

fix interrupting during a quisce on sparc

2007-03-13 00:05:52 -04:00

trace

Rework the way SCons recurses into subdirectories, making it

2007-03-10 23:00:54 -08:00

activity.cc

make our code a little more standards compliant

2007-01-26 18:48:51 -05:00

activity.hh

Update copyright.

2006-06-07 16:02:55 -04:00

base_dyn_inst_impl.hh

Accidently "cleaned" away the NPC parameter to the constructor.

2006-12-16 07:47:33 -05:00

base_dyn_inst.hh

rename store conditional stuff as extra data so it can be used for conditional swaps as well

2007-02-12 13:06:30 -05:00

base.cc

Two fixes:

2007-03-09 10:06:09 -05:00

base.hh

Two fixes:

2007-03-09 10:06:09 -05:00

cpu_models.py

Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.

2006-07-06 12:18:55 -04:00

cpuevent.cc

Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

2006-06-06 17:32:21 -04:00

cpuevent.hh

Make SPARC checkpointing work

2007-01-30 18:25:39 -05:00

exec_context.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

exetrace.cc

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

exetrace.hh

Add setData functions for the new Twin??_t types.

2007-03-07 17:46:06 +00:00

func_unit.cc

Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.

2006-06-16 17:52:15 -04:00

func_unit.hh

Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.

2006-06-16 17:52:15 -04:00

inst_seq.hh

fixes so that M5 will compile under solaris

2006-11-04 21:41:01 -05:00

intr_control.cc

Implement Niagara I/O interface and rework interrupts

2007-03-03 17:22:47 -05:00

intr_control.hh

Implement Niagara I/O interface and rework interrupts

2007-03-03 17:22:47 -05:00

m5legion_interface.h

add fsr to the list of registers we are interested in

2007-01-30 18:27:04 -05:00

op_class.cc

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

op_class.hh

Merge ktlim@zizzer:/bk/newmem

2006-06-02 18:19:50 -04:00

pc_event.cc

remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault

2007-03-12 17:23:08 -04:00

pc_event.hh

Added sim/host.hh for the Addr type.

2006-11-07 05:42:15 -05:00

profile.cc

Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

2006-06-06 17:32:21 -04:00

profile.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

quiesce_event.cc

Add Quiesce trace flag to track CPU quiesce/wakeup events.

2006-10-21 23:32:14 -07:00

quiesce_event.hh

Update copyright.

2006-06-07 16:02:55 -04:00

SConscript

Rework the way SCons recurses into subdirectories, making it

2007-03-10 23:00:54 -08:00

simple_thread.cc

fix segfault when peer owner attempts to use functional port

2007-03-13 17:34:52 -04:00

simple_thread.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

smt.hh

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

static_inst.cc

Move all of the parameters of the Root SimObject so they are

2007-03-06 11:13:43 -08:00

static_inst.hh

While I'm waiting for legion to run make m5 compile with a few more compilers

2007-01-27 15:38:04 -05:00

thread_context.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

thread_state.cc

stop m5 from leaking like a sieve

2007-03-08 18:57:15 -05:00

thread_state.hh

Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.

2006-11-29 16:07:55 -05:00