Giacomo Travaglini 35b6961dcb arch-arm: Fix SMM* instructions ...

A recent clean up patch [1] introduced some bugs in the instruction
implementation of:

SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/42387

Change-Id: I459fe99bd2711e00027e9ef0c7796af7a374a509
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44945
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-05-10 09:08:44 +00:00

..

decoder

arm: Use the common pseudoInst dispatch function.

2020-11-24 05:01:13 +00:00

formats

arm: Use local src and dest reg index arrays.

2021-01-19 00:12:33 +00:00

insts

arch-arm: Fix SMM* instructions

2021-05-10 09:08:44 +00:00

templates

arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-04-10 07:31:23 +00:00

arminstobjparams.isa

arm: Use local src and dest reg index arrays.

2021-01-19 00:12:33 +00:00

bitfields.isa

arch-arm: Implementation of SelfHosted Debug Software step

2020-07-02 11:53:15 +00:00

copyright.txt

arm: Delete authors lists from the arm files.

2020-02-18 03:35:23 +00:00

includes.isa

Revert "arch-arm: Use src/base/fenv.hh instead of raw fenv.h."

2021-04-03 14:03:04 +00:00

main.isa

arm: Use local src and dest reg index arrays.

2021-01-19 00:12:33 +00:00

operands.isa

arch-arm: Simplify the "mult" SIMD instructions with a BitUnion.

2021-04-22 22:12:16 +00:00