137 lines
6.0 KiB
Python
137 lines
6.0 KiB
Python
# Copyright (c) 2009, 2012-2013, 2015-2021 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.options import *
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from m5.SimObject import *
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from m5.util.fdthelper import *
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from m5.objects.System import System
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from m5.objects.ArmSemihosting import ArmSemihosting
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class SveVectorLength(UInt8): min = 1; max = 16
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class ArmSystem(System):
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type = 'ArmSystem'
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cxx_header = "arch/arm/system.hh"
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multi_proc = Param.Bool(True, "Multiprocessor system?")
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gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
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have_security = Param.Bool(False,
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"True if Security Extensions are implemented")
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have_virtualization = Param.Bool(False,
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"True if Virtualization Extensions are implemented")
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have_crypto = Param.Bool(False,
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"True if Crypto Extensions is implemented")
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have_lpae = Param.Bool(True, "True if LPAE is implemented")
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reset_addr = Param.Addr(0x0,
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"Reset address (ARMv8)")
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auto_reset_addr = Param.Bool(True,
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"Determine reset address from kernel entry point if no boot loader")
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highest_el_is_64 = Param.Bool(True,
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"True if the register width of the highest implemented exception level "
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"is 64 bits (ARMv8)")
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phys_addr_range_64 = Param.UInt8(40,
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"Supported physical address range in bits when using AArch64 (ARMv8)")
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have_large_asid_64 = Param.Bool(False,
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"True if ASID is 16 bits in AArch64 (ARMv8)")
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have_sve = Param.Bool(True,
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"True if SVE is implemented (ARMv8)")
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sve_vl = Param.SveVectorLength(1,
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"SVE vector length in quadwords (128-bit)")
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have_lse = Param.Bool(True,
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"True if LSE is implemented (ARMv8.1)")
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have_vhe = Param.Bool(False,
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"True if FEAT_VHE (Virtualization Host Extensions) is implemented")
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have_pan = Param.Bool(True,
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"True if Priviledge Access Never is implemented (ARMv8.1)")
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have_secel2 = Param.Bool(True,
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"True if Secure EL2 is implemented (ARMv8)")
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have_tme = Param.Bool(False,
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"True if transactional memory extension (TME) is implemented")
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semihosting = Param.ArmSemihosting(NULL,
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"Enable support for the Arm semihosting by settings this parameter")
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# Set to true if simulation provides a PSCI implementation
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# This flag will be checked when auto-generating
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# a PSCI node. A client (e.g Linux) would then be able to
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# know if it can use the PSCI APIs
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_have_psci = False
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def generateDtb(self, filename):
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"""
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Autogenerate DTB. Arguments are the folder where the DTB
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will be stored, and the name of the DTB file.
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"""
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state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
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rootNode = self.generateDeviceTree(state)
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fdt = Fdt()
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fdt.add_rootnode(rootNode)
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fdt.writeDtbFile(filename)
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def generateDeviceTree(self, state):
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# Generate a device tree root node for the system by creating the root
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# node and adding the generated subnodes of all children.
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# When a child needs to add multiple nodes, this is done by also
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# creating a node called '/' which will then be merged with the
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# root instead of appended.
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def generateMemNode(mem_range):
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node = FdtNode("memory@%x" % int(mem_range.start))
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node.append(FdtPropertyStrings("device_type", ["memory"]))
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node.append(FdtPropertyWords("reg",
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state.addrCells(mem_range.start) +
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state.sizeCells(mem_range.size()) ))
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return node
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root = FdtNode('/')
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root.append(state.addrCellsProperty())
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root.append(state.sizeCellsProperty())
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# Add memory nodes
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for mem_range in self.mem_ranges:
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root.append(generateMemNode(mem_range))
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for node in self.recurseDeviceTree(state):
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# Merge root nodes instead of adding them (for children
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# that need to add multiple root level nodes)
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if node.get_name() == root.get_name():
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root.merge(node)
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else:
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root.append(node)
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return root
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