derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
3444d5f359bdef91ecebb33c6c241c8e6c673dc0
gem5/src/mem
History
David Hashe 3444d5f359 mem: Hit callback delay fix 
This patch was created by Bihn Pham during his internship at AMD.

There is no need to delay hit callback response messages by a cycle because
the response latency is already incurred in the Ruby protocol. This ensures
correct timing of memory instructions.
2015-07-20 09:15:18 -05:00
..
cache
mem: Add missing clean eviction on uncacheable access
2015-07-30 03:42:25 -04:00
protocol
ruby: re-added the addressToInt slicc interface function
2015-07-20 09:15:18 -05:00
ruby
mem: Hit callback delay fix
2015-07-20 09:15:18 -05:00
slicc
slicc: isinstance bugfix
2015-07-20 09:15:18 -05:00
abstract_mem.cc
mem: Add clean evicts to improve snoop filter tracking
2015-07-03 10:14:37 -04:00
abstract_mem.hh
mem: Dynamically determine page bytes in memory components
2014-10-16 05:49:43 -04:00
AbstractMemory.py
mem: Change AbstractMemory defaults to match the common case
2013-08-19 03:52:33 -04:00
addr_mapper.cc
mem: addr_mapper: restore old address if request not sent
2015-05-30 13:45:17 +02:00
addr_mapper.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
AddrMapper.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
bridge.cc
mem: Fix (ab)use of emplace to avoid temporary object creation
2015-07-13 08:46:28 -04:00
bridge.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
Bridge.py
mem: Tidy up the bridge with const and additional checks
2013-06-27 05:49:49 -04:00
coherent_xbar.cc
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
coherent_xbar.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
comm_monitor.cc
mem: Cleanup CommMonitor in preparation for probe support
2015-07-06 17:08:53 +01:00
comm_monitor.hh
mem: Cleanup CommMonitor in preparation for probe support
2015-07-06 17:08:53 +01:00
CommMonitor.py
mem: Add stack distance statistics to the CommMonitor
2014-12-23 09:31:18 -05:00
dram_ctrl.cc
sim: Refactor and simplify the drain API
2015-07-07 09:51:05 +01:00
dram_ctrl.hh
sim: Refactor and simplify the drain API
2015-07-07 09:51:05 +01:00
DRAMCtrl.py
mem: Increase the default buffer sizes for the DDR4 controller
2015-07-03 10:14:48 -04:00
drampower.cc
mem: Add a GDDR5 DRAM config
2014-12-02 06:07:32 -05:00
drampower.hh
mem: Add DRAMPower wrapping class
2014-07-29 17:29:36 +01:00
dramsim2_wrapper.cc
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
dramsim2_wrapper.hh
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
dramsim2.cc
mem: Updated DRAMSim2 wrapper to new drain API
2015-07-13 08:46:16 -04:00
dramsim2.hh
sim: Refactor and simplify the drain API
2015-07-07 09:51:05 +01:00
DRAMSim2.py
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
external_master.cc
mem: Add ExternalMaster and ExternalSlave ports
2014-10-16 05:49:56 -04:00
external_master.hh
mem: Add ExternalMaster and ExternalSlave ports
2014-10-16 05:49:56 -04:00
external_slave.cc
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
external_slave.hh
mem: Add ExternalMaster and ExternalSlave ports
2014-10-16 05:49:56 -04:00
ExternalMaster.py
mem: Add ExternalMaster and ExternalSlave ports
2014-10-16 05:49:56 -04:00
ExternalSlave.py
mem: Add ExternalMaster and ExternalSlave ports
2014-10-16 05:49:56 -04:00
fs_translating_port_proxy.cc
mem: Use const pointers for port proxy write functions
2014-12-02 06:07:38 -05:00
fs_translating_port_proxy.hh
mem: Use const pointers for port proxy write functions
2014-12-02 06:07:38 -05:00
mem_checker_monitor.cc
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
mem_checker_monitor.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
mem_checker.cc
mem: Fix initial value problem with MemChecker
2015-02-16 03:34:47 -05:00
mem_checker.hh
mem: Add MemChecker and MemCheckerMonitor
2014-12-23 09:31:17 -05:00
mem_object.cc
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
mem_object.hh
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
MemChecker.py
mem: Add MemChecker and MemCheckerMonitor
2014-12-23 09:31:17 -05:00
MemObject.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
mport.cc
MEM: Separate snoops and normal memory requests/responses
2012-04-14 05:45:07 -04:00
mport.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
multi_level_page_table_impl.hh
sim: Refactor the serialization base class
2015-07-07 09:51:03 +01:00
multi_level_page_table.cc
mem: adding a multi-level page table class
2014-04-01 12:18:12 -05:00
multi_level_page_table.hh
sim: Refactor the serialization base class
2015-07-07 09:51:03 +01:00
noncoherent_xbar.cc
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
noncoherent_xbar.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
packet_access.hh
mem: Add const getters for write packet data
2014-12-02 06:07:36 -05:00
packet_queue.cc
mem: Fix (ab)use of emplace to avoid temporary object creation
2015-07-13 08:46:28 -04:00
packet_queue.hh
sim: Refactor and simplify the drain API
2015-07-07 09:51:05 +01:00
packet.cc
mem: Split WriteInvalidateReq into write and invalidate
2015-07-03 10:14:41 -04:00
packet.hh
mem: Transition away from isSupplyExclusive for writebacks
2015-07-30 03:41:40 -04:00
page_table.cc
sim: Refactor the serialization base class
2015-07-07 09:51:03 +01:00
page_table.hh
sim: Refactor the serialization base class
2015-07-07 09:51:03 +01:00
physical.cc
sim: Refactor the serialization base class
2015-07-07 09:51:03 +01:00
physical.hh
sim: Refactor the serialization base class
2015-07-07 09:51:03 +01:00
port_proxy.cc
mem: Clean up Request initialisation
2015-01-22 05:00:53 -05:00
port_proxy.hh
mem: Use const pointers for port proxy write functions
2014-12-02 06:07:38 -05:00
port.cc
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
port.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
qport.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
request.hh
mem: Convert Request static const flags to enums
2015-07-03 10:14:36 -04:00
SConscript
mem: Add a stack distance calculator
2014-12-23 09:31:18 -05:00
se_translating_port_proxy.cc
mem: Use const pointers for port proxy write functions
2014-12-02 06:07:38 -05:00
se_translating_port_proxy.hh
mem: Use const pointers for port proxy write functions
2014-12-02 06:07:38 -05:00
simple_mem.cc
mem: Fix (ab)use of emplace to avoid temporary object creation
2015-07-13 08:46:28 -04:00
simple_mem.hh
sim: Refactor and simplify the drain API
2015-07-07 09:51:05 +01:00
SimpleMemory.py
mem: Add an internal packet queue in SimpleMemory
2013-08-19 03:52:25 -04:00
snoop_filter.cc
mem: Add clean evicts to improve snoop filter tracking
2015-07-03 10:14:37 -04:00
snoop_filter.hh
mem: Delay responses in the crossbar before forwarding
2015-07-03 10:14:44 -04:00
stack_dist_calc.cc
mem: Add a stack distance calculator
2014-12-23 09:31:18 -05:00
stack_dist_calc.hh
mem: Add a stack distance calculator
2014-12-23 09:31:18 -05:00
StackDistCalc.py
mem: Add a stack distance calculator
2014-12-23 09:31:18 -05:00
tport.cc
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
tport.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
xbar.cc
sim: Refactor and simplify the drain API
2015-07-07 09:51:05 +01:00
xbar.hh
sim: Refactor and simplify the drain API
2015-07-07 09:51:05 +01:00
XBar.py
mem: Move crossbar default latencies to subclasses
2015-03-02 04:00:47 -05:00