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gem5/src/dev/SConscript
Gabe Black fbd0722de4 fastmodel,dev: Replace the reset port with a Signal*Port<bool>.
The ResetRequestPort and ResetResponsePort have a few problems:

1. A reset signal should happen during the time a reset is asserted,
or in other words the device should stay in reset and not doing
anything while reset is asserted. It should not immediately restart
execution while the reset is still held.

2. These names are misleading, since there is no response. These names
are inherited from other port types where there is an actual response.

There is a new generic SignalSourcePort and SignalSinkPort set of port
classes which are templated on the type of signal they propogate, and
which can be used in place of reset ports in c++. These ports can
still have a specialized role which will ensure that only reset ports
are connected to each other for a form of type checking, although
the underlying c++ instances are more interoperable than that.

Change-Id: Id98bef901ab61ac5b200dbbe49439bb2d2e6c57f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66675
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-12-16 07:19:05 +00:00

58 lines
2.2 KiB
Python

# -*- mode:python -*-
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
SimObject('Device.py', sim_objects=[
'PioDevice', 'BasicPioDevice', 'DmaDevice', 'DmaVirtDevice', 'IsaFake'])
Source('io_device.cc')
Source('isa_fake.cc')
Source('dma_device.cc')
Source('dma_virt_device.cc')
SimObject('IntPin.py', sim_objects=[])
SimObject('ResetPort.py', sim_objects=[])
DebugFlag('IsaFake')
DebugFlag('DMA')
SimObject('Platform.py', sim_objects=['Platform'])
Source('platform.cc')
SimObject('BadDevice.py', sim_objects=['BadDevice'])
Source('baddev.cc')
Source('intel_8254_timer.cc')
Source('mc146818.cc')
Source('pixelpump.cc')
DebugFlag('Intel8254Timer')
DebugFlag('MC146818')
GTest('reg_bank.test', 'reg_bank.test.cc')