7bc9b0175f
Enable a gem5 system to be an SST::Component.
This change includes,
- SST::gem5Component: responsible for,
- initializing the Python environment for gem5
- instantiating gem5 SimObjects
- connecting SST::SSTResponderSubComponent to
gem5::OutgoingRequestBridge
- hanlding the gem5 event queue (no thread-synchronization)
- handling executing gem5 events
- SST::SSTResponderSubComponent: responsible for,
- receiving gem5 requests and sending the requests to
memory.
- sending responses to the corresponding
gem5::OutgoingRequestBridge.
- SST::SSTResponder: owned by SSTResponderSubComponent, the
actual actor that sends gem5's requests to memory.
- gem5::OutgoingRequestBridge: receives the requests from
gem5 and sends them to SST. This SimObject allows the initialization
requests to be cached and the receiver could query the
initialization data later on.
- gem5::SSTResponderInterface: the interface specifying how SST
communicates with gem5.
- A working example of a gem5/SST setup.
More information is available at ext/sst/README.md.
For installation instructions, please refer to ext/sst/INSTALL.md.
Change-Id: I6b81260ef825415bcfe72b8a078854f4c94de782
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50468
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
86 lines
3.3 KiB
Markdown
86 lines
3.3 KiB
Markdown
# Using gem5 in an SST simulation
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## Overview
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This directory contains the library needed to use gem5 TimingSimpleCPU model in
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an SST-driven simulation.
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When compiled, the gem5 library for SST `libgem5.so` will be generated,
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containing the `libgem5_*.so` as well as the gem5 Component and the
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SST Responder SubComponent.
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```text
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On/Off-chip devs TimingSimpleCPU
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^ ^ ^
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v v v
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==================================== [gem5::NonCoherentXBar]
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^ [OutgoingRequestBridge]
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gem5_system_port |
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[OutgoingRequestBridge] ^ |
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[SSTResponder] v v [SSTResponder]
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gem5 Component {SSTResponderSubComponent, SSTResponderSubComponent}
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^ ^
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v v
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================================== [SST Bus]
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^
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v
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SST cache <----> SST memory
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```
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## Components and SubComponents
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- gem5 Component has the following responsibilities,
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- initializing the gem5 Python environment
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- instantiating/setting-up the gem5 SimObjects as specified by the gem5
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configuration
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- connect every SSTResponderSubComponent to the corresponding
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OutgoingRequestBridge
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- handling a gem5 event queue (with all thread-synchronization barriers
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removed)
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- handling executions of gem5 events when it has clockTick yielded by SST
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**Note:** there should only be one gem5 Component per process.
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- SSTResponderSubComponent has the responsibity of receiving requests from
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gem5, translating requests to an SST Request and sending it to SSTResponder.
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Upon receiving a response from the memory interface, SSTResponderSubComponent
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will translate the response to a gem5 Packet and send it to the its
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OutgoingRequestBridge.
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- SSTResponder is owned by SSTResponderSubComponent. The responder will receive
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the request from the SubComponent and send it to the SST memory hierarchy.
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## Installation
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See `INSTALL.md`.
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## Running an example simulation
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Downloading the built bootloader containing a Linux Kernel and a workload,
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```sh
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wget http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit
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```
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Running the simulation
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```sh
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sst sst/example.py
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```
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`bbl-busybox-boot-exit` contains an m5 binary, and `m5 exit` will be called
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upon the booting process reaching the early userspace.
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More information about building a bootloader containing a Linux Kernel and a
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customized workload is available at
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[https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-boot-exit-nodisk/].
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## Notes
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- SwapReq from gem5 requires reading from memory and writing to memory.
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We handle the request in SST in a way that, when SST gets the response
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from memory, SST will send that response to gem5, while SST will send
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a write request with modified data to memory.
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