de7337a32a
In order to fix several regression failures [1] the master/slave terminology in src/cpu/BaseCPU.py was reintroduced [2]. This patch is addressing the issue by providing 2 different ways of connecting cpu ports: *) connectBus: The method assumes an object with a bus interface is passed as an argument, therefore it tries to bind cpu ports to the bus.mem_side_ports and bus.cpu_side_ports *) connectAllPorts: No assumption on the port owning device is made. The method simply accepts ports as arguments which will be directly connected to the peer cpu ports This will be used for example by ruby Sequencers [1]: https://gem5.atlassian.net/browse/GEM5-775 [2]: https://gem5-review.googlesource.com/c/public/gem5/+/34495 Change-Id: I715ab8471621d6e5eb36731d7eaefbedf9663a71 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52584 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
429 lines
15 KiB
Python
429 lines
15 KiB
Python
# Copyright (c) 2016-2017, 2019, 2021 Arm Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# System components used by the bigLITTLE.py configuration script
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import m5
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from m5.objects import *
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m5.util.addToPath('../../')
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from common.Caches import *
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from common import ObjectList
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have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
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have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()
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class L1I(L1_ICache):
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tag_latency = 1
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data_latency = 1
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response_latency = 1
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mshrs = 4
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tgts_per_mshr = 8
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size = '48kB'
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assoc = 3
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class L1D(L1_DCache):
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tag_latency = 2
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data_latency = 2
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response_latency = 1
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mshrs = 16
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tgts_per_mshr = 16
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size = '32kB'
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assoc = 2
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write_buffers = 16
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class WalkCache(PageTableWalkerCache):
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tag_latency = 4
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data_latency = 4
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response_latency = 4
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mshrs = 6
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tgts_per_mshr = 8
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size = '1kB'
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assoc = 8
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write_buffers = 16
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class L2(L2Cache):
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tag_latency = 12
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data_latency = 12
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response_latency = 5
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mshrs = 32
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tgts_per_mshr = 8
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size = '1MB'
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assoc = 16
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write_buffers = 8
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clusivity='mostly_excl'
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class L3(Cache):
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size = '16MB'
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assoc = 16
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tag_latency = 20
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data_latency = 20
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response_latency = 20
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mshrs = 20
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tgts_per_mshr = 12
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clusivity='mostly_excl'
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class MemBus(SystemXBar):
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badaddr_responder = BadAddr(warn_access="warn")
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default = Self.badaddr_responder.pio
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class CpuCluster(SubSystem):
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def __init__(self, system, num_cpus, cpu_clock, cpu_voltage,
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cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
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super(CpuCluster, self).__init__()
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self._cpu_type = cpu_type
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self._l1i_type = l1i_type
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self._l1d_type = l1d_type
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self._wcache_type = wcache_type
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self._l2_type = l2_type
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assert num_cpus > 0
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self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
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self.clk_domain = SrcClockDomain(clock=cpu_clock,
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voltage_domain=self.voltage_domain)
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self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
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clk_domain=self.clk_domain)
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for idx in range(num_cpus) ]
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for cpu in self.cpus:
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.socket_id = system.numCpuClusters()
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system.addCpuCluster(self, num_cpus)
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def requireCaches(self):
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return self._cpu_type.require_caches()
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def memoryMode(self):
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return self._cpu_type.memory_mode()
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def addL1(self):
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for cpu in self.cpus:
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l1i = None if self._l1i_type is None else self._l1i_type()
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l1d = None if self._l1d_type is None else self._l1d_type()
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iwc = None if self._wcache_type is None else self._wcache_type()
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dwc = None if self._wcache_type is None else self._wcache_type()
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cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
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def addL2(self, clk_domain):
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if self._l2_type is None:
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return
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self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
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self.l2 = self._l2_type()
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for cpu in self.cpus:
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cpu.connectCachedPorts(self.toL2Bus.cpu_side_ports)
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self.toL2Bus.mem_side_ports = self.l2.cpu_side
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def addPMUs(self, ints, events=[]):
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"""
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Instantiates 1 ArmPMU per PE. The method is accepting a list of
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interrupt numbers (ints) used by the PMU and a list of events to
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register in it.
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:param ints: List of interrupt numbers. The code will iterate over
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the cpu list in order and will assign to every cpu in the cluster
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a PMU with the matching interrupt.
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:type ints: List[int]
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:param events: Additional events to be measured by the PMUs
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:type events: List[Union[ProbeEvent, SoftwareIncrement]]
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"""
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assert len(ints) == len(self.cpus)
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for cpu, pint in zip(self.cpus, ints):
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int_cls = ArmPPI if pint < 32 else ArmSPI
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for isa in cpu.isa:
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isa.pmu = ArmPMU(interrupt=int_cls(num=pint))
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isa.pmu.addArchEvents(cpu=cpu,
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itb=cpu.mmu.itb, dtb=cpu.mmu.dtb,
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icache=getattr(cpu, 'icache', None),
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dcache=getattr(cpu, 'dcache', None),
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l2cache=getattr(self, 'l2', None))
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for ev in events:
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isa.pmu.addEvent(ev)
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def connectMemSide(self, bus):
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try:
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self.l2.mem_side = bus.cpu_side_ports
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except AttributeError:
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for cpu in self.cpus:
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cpu.connectCachedPorts(bus.cpu_side_ports)
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class AtomicCluster(CpuCluster):
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def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
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cpu_config = [ ObjectList.cpu_list.get("AtomicSimpleCPU"), None,
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None, None, None ]
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super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
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cpu_voltage, *cpu_config)
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def addL1(self):
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pass
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class KvmCluster(CpuCluster):
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def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
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cpu_config = [ ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,
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None, None ]
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super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
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cpu_voltage, *cpu_config)
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def addL1(self):
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pass
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class FastmodelCluster(SubSystem):
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def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
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super(FastmodelCluster, self).__init__()
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# Setup GIC
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gic = system.realview.gic
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gic.sc_gic.cpu_affinities = ','.join(
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[ '0.0.%d.0' % i for i in range(num_cpus) ])
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# Parse the base address of redistributor.
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redist_base = gic.get_redist_bases()[0]
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redist_frame_size = 0x40000 if gic.sc_gic.has_gicv4_1 else 0x20000
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gic.sc_gic.reg_base_per_redistributor = ','.join([
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'0.0.%d.0=%#x' % (i, redist_base + redist_frame_size * i)
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for i in range(num_cpus)
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])
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gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m)
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gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm,
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gem5=system.iobus.cpu_side_ports)
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gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.mem_side_ports)
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gic_g2t.addr_ranges = gic.get_addr_ranges()
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gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm)
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gic.amba_s = gic_t2a.amba
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system.gic_hub = SubSystem()
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system.gic_hub.gic_a2t = gic_a2t
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system.gic_hub.gic_t2g = gic_t2g
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system.gic_hub.gic_g2t = gic_g2t
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system.gic_hub.gic_t2a = gic_t2a
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self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
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self.clk_domain = SrcClockDomain(clock=cpu_clock,
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voltage_domain=self.voltage_domain)
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# Setup CPU
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assert num_cpus <= 4
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CpuClasses = [FastModelCortexA76x1, FastModelCortexA76x2,
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FastModelCortexA76x3, FastModelCortexA76x4]
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CpuClass = CpuClasses[num_cpus - 1]
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cpu = CpuClass(GICDISABLE=False)
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for core in cpu.cores:
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core.semihosting_enable = False
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core.RVBARADDR = 0x10
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core.redistributor = gic.redistributor
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core.createThreads()
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core.createInterruptController()
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self.cpus = [ cpu ]
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a2t = AmbaToTlmBridge64(amba=cpu.amba)
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t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.cpu_side_ports)
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system.gic_hub.a2t = a2t
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system.gic_hub.t2g = t2g
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system.addCpuCluster(self, num_cpus)
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def requireCaches(self):
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return False
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def memoryMode(self):
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return 'atomic_noncaching'
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def addL1(self):
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pass
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def addL2(self, clk_domain):
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pass
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def connectMemSide(self, bus):
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pass
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class BaseSimpleSystem(ArmSystem):
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cache_line_size = 64
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def __init__(self, mem_size, platform, **kwargs):
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super(BaseSimpleSystem, self).__init__(**kwargs)
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self.voltage_domain = VoltageDomain(voltage="1.0V")
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self.clk_domain = SrcClockDomain(
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clock="1GHz",
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voltage_domain=Parent.voltage_domain)
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if platform is None:
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self.realview = VExpress_GEM5_V1()
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else:
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self.realview = platform
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if hasattr(self.realview.gic, 'cpu_addr'):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.terminal = Terminal()
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self.vncserver = VncServer()
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self.iobus = IOXBar()
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# Device DMA -> MEM
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self.mem_ranges = self.getMemRanges(int(Addr(mem_size)))
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self._clusters = []
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self._num_cpus = 0
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def getMemRanges(self, mem_size):
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"""
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Define system memory ranges. This depends on the physical
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memory map provided by the realview platform and by the memory
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size provided by the user (mem_size argument).
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The method is iterating over all platform ranges until they cover
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the entire user's memory requirements.
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"""
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mem_ranges = []
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for mem_range in self.realview._mem_regions:
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size_in_range = min(mem_size, mem_range.size())
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mem_ranges.append(
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AddrRange(start=mem_range.start, size=size_in_range))
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mem_size -= size_in_range
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if mem_size == 0:
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return mem_ranges
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raise ValueError("memory size too big for platform capabilities")
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def numCpuClusters(self):
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return len(self._clusters)
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def addCpuCluster(self, cpu_cluster, num_cpus):
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assert cpu_cluster not in self._clusters
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assert num_cpus > 0
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self._clusters.append(cpu_cluster)
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self._num_cpus += num_cpus
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def numCpus(self):
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return self._num_cpus
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def addCaches(self, need_caches, last_cache_level):
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if not need_caches:
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(self.membus)
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return
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cluster_mem_bus = self.membus
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assert last_cache_level >= 1 and last_cache_level <= 3
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for cluster in self._clusters:
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cluster.addL1()
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if last_cache_level > 1:
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for cluster in self._clusters:
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cluster.addL2(cluster.clk_domain)
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if last_cache_level > 2:
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max_clock_cluster = max(self._clusters,
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key=lambda c: c.clk_domain.clock[0])
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self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
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self.toL3Bus = L2XBar(width=64)
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self.toL3Bus.mem_side_ports = self.l3.cpu_side
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self.l3.mem_side = self.membus.cpu_side_ports
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cluster_mem_bus = self.toL3Bus
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(cluster_mem_bus)
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class SimpleSystem(BaseSimpleSystem):
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"""
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Meant to be used with the classic memory model
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"""
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def __init__(self, caches, mem_size, platform=None, **kwargs):
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super(SimpleSystem, self).__init__(mem_size, platform, **kwargs)
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self.membus = MemBus()
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# CPUs->PIO
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self.iobridge = Bridge(delay='50ns')
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self._caches = caches
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if self._caches:
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self.iocache = IOCache(addr_ranges=self.mem_ranges)
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else:
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self.dmabridge = Bridge(delay='50ns',
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ranges=self.mem_ranges)
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def connect(self):
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self.iobridge.mem_side_port = self.iobus.cpu_side_ports
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self.iobridge.cpu_side_port = self.membus.mem_side_ports
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if self._caches:
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self.iocache.mem_side = self.membus.cpu_side_ports
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self.iocache.cpu_side = self.iobus.mem_side_ports
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else:
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self.dmabridge.mem_side_port = self.membus.cpu_side_ports
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self.dmabridge.cpu_side_port = self.iobus.mem_side_ports
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if hasattr(self.realview.gic, 'cpu_addr'):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.realview.attachOnChipIO(self.membus, self.iobridge)
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self.realview.attachIO(self.iobus)
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self.system_port = self.membus.cpu_side_ports
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def attach_pci(self, dev):
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self.realview.attachPciDevice(dev, self.iobus)
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class ArmRubySystem(BaseSimpleSystem):
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"""
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Meant to be used with ruby
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"""
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def __init__(self, mem_size, platform=None, **kwargs):
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super(ArmRubySystem, self).__init__(mem_size, platform, **kwargs)
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self._dma_ports = []
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self._mem_ports = []
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def connect(self):
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self.realview.attachOnChipIO(self.iobus,
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dma_ports=self._dma_ports, mem_ports=self._mem_ports)
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self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
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for cluster in self._clusters:
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for i, cpu in enumerate(cluster.cpus):
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self.ruby._cpu_ports[i].connectCpuPorts(cpu)
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def attach_pci(self, dev):
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self.realview.attachPciDevice(dev, self.iobus,
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dma_ports=self._dma_ports)
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