Gabe Black 2c3c7df5fc fastmodel: Implement inst count events in the IRIS thread contexts. ...

These use the IRIS stepping API.

Change-Id: Ib45744cb0928fece664187e4df6b25b064b19f0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22115
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-11-06 22:05:29 +00:00

..

arch

fastmodel: Implement inst count events in the IRIS thread contexts.

2019-11-06 22:05:29 +00:00

base

base: Name segments after their index

2019-10-30 09:15:04 +00:00

cpu

cpu: Use std::array for registers in SimpleThread.

2019-11-06 01:41:12 +00:00

dev

dev-arm: optional instantiation of GICv3 ITS

2019-11-05 09:27:30 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

…

gpu-compute

gpu-compute: Fix overriden errors

2019-09-20 22:42:31 +00:00

kern

kern: When dumping dmesg, detect the byte order dynamically.

2019-10-30 22:29:23 +00:00

learning_gem5

mem-ruby: Allow Ruby to use all replacement policies in Classic

2019-10-11 03:29:29 +00:00

mem

mem-ruby: Reset Ruby Sequencer Outstanding Requests stats

2019-11-05 12:28:24 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

misc: Added line wrapping functionality for Sim-Object desc

2019-09-30 19:50:26 +00:00

sim

arch,sim: Make copyStringArray take an explicit endianness.

2019-10-30 22:29:23 +00:00

systemc

systemc: Make TLM port wrappers for tlm_base_(target|initiator)_socket.

2019-09-17 19:07:59 +00:00

unittest

tests: Added GTests for base/str.cc

2019-10-24 16:25:09 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Move the marshal binary to the build directory

2019-05-21 15:46:50 +00:00