b489e49c68
If there's no more compatible workload than the base SEWorkload class it will fall back to that for now. Change-Id: Id27172c3074a7976823a891878ab9eecf6246c47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33901 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
103 lines
3.8 KiB
Python
103 lines
3.8 KiB
Python
# Copyright (c) 2020 The Regents of the University of California
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# All Rights Reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import m5
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from m5.objects import *
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from caches import *
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import sys
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import argparse
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parser = argparse.ArgumentParser(description='m5threads atomic tester')
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parser.add_argument('--cpu-type', default='DerivO3CPU')
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parser.add_argument('--num-cores', default='8')
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parser.add_argument('--cmd')
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args = parser.parse_args()
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root = Root(full_system = False)
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root.system = System()
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root.system.workload = SEWorkload.init_compatible(args.cmd)
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root.system.clk_domain = SrcClockDomain()
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root.system.clk_domain.clock = '3GHz'
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root.system.clk_domain.voltage_domain = VoltageDomain()
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root.system.mem_mode = 'timing'
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root.system.mem_ranges = [AddrRange('512MB')]
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if args.cpu_type == 'DerivO3CPU':
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root.system.cpu = [DerivO3CPU(cpu_id = i)
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for i in range (int(args.num_cores))]
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elif args.cpu_type == 'TimingSimpleCPU':
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root.system.cpu = [TimingSimpleCPU(cpu_id=i)
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for i in range(int(args.num_cores))]
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else:
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print("ERROR: CPU Type '" + args.cpu_type + "' not supported")
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sys.exit(1)
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root.system.membus = SystemXBar()
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root.system.membus.badaddr_responder = BadAddr()
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root.system.membus.default = root.system.membus.badaddr_responder.pio
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root.system.system_port = root.system.membus.slave
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process = Process(executable = args.cmd,
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cmd = [args.cmd, str(args.num_cores)])
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for cpu in root.system.cpu:
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cpu.workload = process
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cpu.createThreads()
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cpu.createInterruptController()
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# Create a memory bus, a coherent crossbar, in this case
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cpu.l2bus = L2XBar()
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# Create an L1 instruction and data cache
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cpu.icache = L1ICache()
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cpu.dcache = L1DCache()
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# Connect the instruction and data caches to the CPU
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cpu.icache.connectCPU(cpu)
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cpu.dcache.connectCPU(cpu)
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# Hook the CPU ports up to the l2bus
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cpu.icache.connectBus(cpu.l2bus)
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cpu.dcache.connectBus(cpu.l2bus)
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# Create an L2 cache and connect it to the l2bus
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cpu.l2cache = L2Cache()
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cpu.l2cache.connectCPUSideBus(cpu.l2bus)
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# Connect the L2 cache to the L3 bus
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cpu.l2cache.connectMemSideBus(root.system.membus)
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root.system.mem_ctrl = DDR3_1600_8x8()
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root.system.mem_ctrl.range = root.system.mem_ranges[0]
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root.system.mem_ctrl.port = root.system.membus.master
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m5.instantiate()
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exit_event = m5.simulate()
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