Giacomo Travaglini e333a77c12 arch-arm: Remove _Xt postfix from TLBI instructions ...

The Xt is not part of the architectural name of the register
and it was likely added with the introduction of extended
register (Xt) TLBIs in Armv8 to differentiate them with
the old Armv7 ones.

The use of _Xt was not consistent anyway: newer TLBIs were
already omitting it.

Change-Id: Ic805340ffa7b5770e3b75a71bfb76e055e651f8b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2024-02-01 13:43:26 +00:00

..

ArmCapstone.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

capstone.cc

arch-arm: Implement a CapstoneDisassembler for Arm

2023-10-20 09:27:51 +01:00

capstone.hh

arch-arm: Implement a CapstoneDisassembler for Arm

2023-10-20 09:27:51 +01:00

SConscript

arch-arm: Only build ArmCapstoneDisassembler when ISA is arm (#553)

2023-12-03 13:22:11 -08:00

tarmac_base.cc

arch-arm: disassemble member variable not used by TarmacParser

2023-10-20 09:27:50 +01:00

tarmac_base.hh

arch-arm: disassemble member variable not used by TarmacParser

2023-10-20 09:27:50 +01:00

tarmac_parser.cc

arch-arm: Remove _Xt postfix from TLBI instructions

2024-02-01 13:43:26 +00:00

tarmac_parser.hh

misc: Replace namespace Trace with lowercase trace

2022-10-02 16:30:15 +00:00

tarmac_record_v8.cc

arch-arm: Fix formatting of v8 Tarmac Register records

2023-04-13 21:09:36 +00:00

tarmac_record_v8.hh

misc: Replace namespace Trace with lowercase trace

2022-10-02 16:30:15 +00:00

tarmac_record.cc

arch-arm: Disassemble through InstDisassembler in TarmacTracer

2023-10-20 09:27:51 +01:00

tarmac_record.hh

arch-arm: disassemble member variable not used by TarmacParser

2023-10-20 09:27:50 +01:00

tarmac_tracer.cc

arch-arm: Allow TarmacTracer to dump trace to a file

2022-10-27 15:33:06 +00:00

tarmac_tracer.hh

arch-arm: Pass a reference of the parent tracer to TarmacContext

2023-10-20 09:27:51 +01:00

TarmacTrace.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00